Register Descriptions - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)

Document ID: PG169
Release Date: 2024-06-05
Version: 2.4 English

Table 1. CORE_VERSION_REG (Address: 0x0000)
Bits	Default	Type	Description
7:0	minor	R	Current version of the core in the format “major.minor.” For example, core version 1.9. Bits[7:0] represents minor version that is 9. Bits[15:8] represents major version that is 1.
15:8	major	R
31:16	0	N/A	Reserved

Table 2. GT_RESET_REG (Address: 0x0004)
Bits	Default	Type	Description
0	0	RW	gt_reset_all. A write of 1 issues a RESET to the GTs. This is a clear on write register.
31:1	0	N/A	Reserved

Table 3. RESET_REG (Address: 0x0008)
Bits	Default	Type	Description
11:0	0	RW	usr_rx_serdes_reset. Unused PCS bits are RESERVED. A write of 1 in a given bit location puts that PCS lane logic into reset.
12	0	RW	usr_tx_serdes_refclk_reset. A write of 1 puts the TX SerDes Refclk path in reset.
29:13	0	N/A	Reserved
30	0	RW	usr_rx_reset. RX core reset. A write of 1 puts the RX path in reset.
31	0	RW	usr_tx_reset. TX core reset. A write of 1 puts the TX path in reset.

Table 4. CONFIGURATION_TX_REG (Address: 0x000C)
Bits	Default	Type	Description
0	0	RW	ctl_tx_enable
8:1	0	RW	ctl_tx_mubits
31:9	0	N/A	Reserved

Table 5. CONFIGURATION_TX_DIAGWORD_REG (Address: 0x0010)
Bits	Default	Type	Description
0	0	RW	ctl_tx_diagword_intfstat
12:1	0	RW	ctl_tx_diagword_lanestat
31:13	0	N/A	Reserved

Table 6. CONFIGURATION_RX_REG (Address: 0x0014)
Bits	Default	Type	Description
0	0	RW	ctl_rx_force_resync
31:1	0	N/A	Reserved

Table 7. GT_LOOPBACK_REG (Address: 0x0018)
Bits	Default	Type	Description
0	0	RW	axi_gt_loopback 0 is for Normal operation 1 is for Near End PMA loopback
31:1	0	N/A	Reserved

Table 8. STAT_TX_STATUS_REG (Address: 0x0200)
Bits	Default	Type	Description
0	0	R/LH	stat_tx_underflow_err
1	0	R/LH	stat_tx_overflow_err
2	0	R/LH	stat_tx_burst_err
3	1	R/LL	stat_tx_errinj_biterr_done
31:4	0	N/A	Reserved

Table 9. STAT_RX_STATUS_REG (Address: 0x0204)
Bits	Default	Type	Description
0	1	R/LL	stat_rx_aligned. Default value is the value after reset.
1	0	R/LH	stat_rx_aligned_err
2	0	R/LH	stat_rx_misaligned
3	0	R/LH	stat_rx_msop_err
4	0	R/LH	stat_rx_meop_err
5	0	R/LH	stat_rx_burst_err
6	0	R/LH	stat_rx_burstmax_err
7	0	R/LH	stat_rx_overflow_err
19:8	12’hFFF	R/LL	stat_rx_word_sync
31:20	0	N/A	Reserved

Table 10. STAT_RX_DIAGWORD_REG (Address: 0x0208)
Bits	Default	Type	Description
11:0	12’hFFF	R/LL	stat_rx_diagword_lanestat
23:12	12’hFFF	R/LL	stat_rx_diagword_intfstat
31:24	0	N/A	Reserved

Table 11. STAT_RX_MUBITS_REG (Address: 0x020C)
Bits	Default	Type	Description
7:0	0	R/LH	stat_rx_mubits
31:8	0	N/A	Reserved

Table 12. STAT_RX_SYNCED_REG (Address: 0x0210)
Bits	Default	Type	Description
11:0	12’hFFF	R/LL	stat_rx_synced
31:12	0	N/A	Reserved

Table 13. STAT_RX_SYNCED_ERR_REG (Address: 0x0214)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_synced_err
31:12	0	N/A	Reserved

Table 14. STAT_RX_MF_ERR_REG (Address: 0x0218)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_mf_err
31:12	0	N/A	Reserved

Table 15. STAT_RX_MF_LEN_ERR_REG (Address: 0x021C)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_mf_len_err
31:12	0	N/A	Reserved

Table 16. STAT_RX_MF_REPEAT_ERR_REG (Address: 0x0220)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_mf_repeat_err
31:12	0	N/A	Reserved

Table 17. STAT_RX_FRAMING_ERR_REG (Address: 0x0224)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_framing_err
31:12	0	N/A	Reserved

Table 18. STAT_RX_DESCRAM_ERR_REG (Address: 0x0228)
Bits	Default	Type	Description
11:0	0	R/LH	stat_rx_descram_err
31:12	0	N/A	Reserved

Table 19. TICK_REG (Address: 0x02B0)
Bits	Default	Type	Description
0	0	WO/SC	tick_reg. Writing a 1 to the Tick bit triggers a snapshot of all the Statistics Counters into their readable registers. The bit self-clears, thus only a single write is required by the user logic.
31:1	0	N/A	Reserved