The protocol bypass (lane logic only) interface helps the Integrated Interlaken IP core bypass the protocol logic and enables direct user access to the lane logic function. This allows you to build a fully featured Interlaken core by leveraging existing integrated lane logic and soft protocol logic.
On UltraScale devices, the maximum rate for each lane through the protocol bypass interface is 12.5 Gb/s for a maximum aggregate throughput of 150 Gb/s (12 x 12.5 Gb/s). Whereas on UltraScale+ devices, each lane supports up to 25.78125 Gb/s through the protocol bypass interface for a maximum aggregate throughput of 300 Gb/s (12 x 25.78125 Gb/s). The interface to the transceivers is a 64-bit "RAW" interface, with the gearbox function performed in the Integrated Interlaken IP core. All lanes support 64B/67B encoding/decoding, synchronization, and scrambling required by the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
On AMD Virtex™ UltraScale+™ devices, the protocol bypass (lane logic only) interface can be used along with AMD soft protocol logic to build Interlaken cores with overall bandwidth of up to 300 Gb/s. For more details, see the Interlaken 600G LogiCORE IP Product Guide (PG209).