The integrated IP core for Interlaken is a single core capable of up to 150 Gb/s. The core connects to the serial transceivers at defined rates up to 12.5 Gb/s with GTH transceivers and up to 25.78125 Gb/s with GTY transceivers.
The following table defines the integrated IP core for Interlaken solutions.
| Lane Width | Line Rate | SerDes | SerDes Width |
|---|---|---|---|
| x1 – x12 | Up to 12.5 Gb/s | GTH/GTY | 64-bit |
| x1 – x6 | Up to 25.78125 Gb/s | GTY | 64-bit |
The Interlaken core internally instantiates the Interlaken integrated IP core (ILKN). The core also instantiates GTH/GTY and an example of how the two integrated IP cores are connected together, along with the reset and clocking for those integrated IP cores.
The following figure illustrates the following interfaces to the Integrated Interlaken IP core.
- Serial transceiver interface
- User-side LBUS interface
- Lane logic bus interface
- Status/Control interface
- DRP interface used for configuration
Figure 1. Interlaken Integrated IP Core Block Diagram
