Port Descriptions - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)
Document ID
PG169
Release Date
2024-06-05
Version
2.4 English

The following table describes the AMD UltraScale+™ and AMD UltraScale™ device Interlaken (ILKN) primitive ports.

Table 1. UltraScale+ and UltraScale Device Interlaken Primitive Ports
Name I/O Clock Domain Description
Transceiver I/O
RX_SERDES_DATA0[63:0] I rx_serdes_clk[0] Data bus from the serial transceiver macros for lane0. There are 12 rx_serdes_data buses; one bus for each serial transceiver lane and each bus has 64 bits. By definition, Bit[63] is the first bit received by the Interlaken core. Bit[0] is the last bit received.
RX_SERDES_DATA1[63:0] I rx_serdes_clk[1] Data bus from the serial transceiver macros for lane1.
RX_SERDES_DATA2[63:0] I rx_serdes_clk[2] Data bus from the serial transceiver macros for lane2.
RX_SERDES_DATA3[63:0] I rx_serdes_clk[3] Data bus from the serial transceiver macros for lane3.
RX_SERDES_DATA4[63:0] I rx_serdes_clk[4] Data bus from the serial transceiver macros for lane4.
RX_SERDES_DATA5[63:0] I rx_serdes_clk[5] Data bus from the serial transceiver macros for lane5.
RX_SERDES_DATA6[63:0] I rx_serdes_clk[6] Data bus from the serial transceiver macros for lane6.
RX_SERDES_DATA7[63:0] I rx_serdes_clk[7] Data bus from the serial transceiver macros for lane7.
RX_SERDES_DATA8[63:0] I rx_serdes_clk[8] Data bus from the serial transceiver macros for lane8.
RX_SERDES_DATA9[63:0] I rx_serdes_clk[9] Data bus from the serial transceiver macros for lane9.
RX_SERDES_DATA10[63:0] I rx_serdes_clk[10] Data bus from the serial transceiver macros for lane10.
RX_SERDES_DATA11[63:0] I rx_serdes_clk[11] Data bus from the serial transceiver macros for lane11.
TX_SERDES_DATA0[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane0. There are 12 tx_serdes_data buses; one bus for each serial transceiver lane and each bus has 64 bits. By definition, Bit[63] is the first bit transmitted by the Interlaken core. Bit[0] is the last bit transmitted.
TX_SERDES_DATA1[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane1.
TX_SERDES_DATA2[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane2.
TX_SERDES_DATA3[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane3.
TX_SERDES_DATA4[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane4.
TX_SERDES_DATA5[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane5.
TX_SERDES_DATA6[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane6.
TX_SERDES_DATA7[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane7.
TX_SERDES_DATA8[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane8.
TX_SERDES_DATA9[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane9.
TX_SERDES_DATA10[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane10.
TX_SERDES_DATA11[63:0] O tx_serdes_refclk Data bus to the serial transceiver macros for lane11.
RX_SERDES_CLK[11:0] I Recovered clock of each serial transceiver lane. The rx_serdes_data bus for each lane is synchronized to the positive edge of the corresponding bit of this bus.
RX_SERDES_RESET[11:0] I Async Reset for each RX serial transceiver lane. The recovered clock for each serial transceiver lane has associated with it an active-High reset. This signal should be 1 whenever the associated recovered clock is not operating at the correct frequency. The RX_SERDES_RESET signals should be held in reset until the GT (also known as serial transceiver) initialization is complete and the clocks are stable.
TX_SERDES_REFCLK I Reference clock for the TX datapath. This clock must be frequency locked to the TX SERDES clock inputs. Typically, the same reference clock used to drive the TX serial transceiver is connected to this input.
TX_SERDES_REFCLK_RESET I Async Reset for TX Reference clock. This active-High signal should 1 whenever the tx_serdes_refclk input is not operating at the correct frequency as indicated by the transceiver phase-locked (PLL) lock signal.
LBUS Interface – Clock/Reset/Control Signals
CORE_CLK I 300/412 MHz core clock. The minimum core clock frequency is 300 MHz for 12 x 12.5 Gb/s mode.
LBUS_CLK I Rate-adapting FIFO clock for the user side logic. LBUS signals are synchronized to this clock.
RX_RESET I Async Asynchronous reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until all of the clocks for the RX path are fully active. These clocks are CORE_CLK, LBUS_CLK and rx_serdes_clk[11:0]. The Interlaken core handles synchronizing the rx_reset input to the appropriate clock domains within the core.
TX_RESET I Async Asynchronous reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until all of the clocks for the TX path are fully active. These clocks are CORE_CLK, LBUS_CLK, and tx_serdes_refclk. The Interlaken core handles synchronizing the tx_reset input to the appropriate clock domains within the core.
RX_OVFOUT O lbus_clk Receive LBUS overflow. If this signal is asserted, it means that the LBUS clock is too slow for the incoming data stream. The LBUS bandwidth must be greater than the Interlaken bandwidth.
RX_DATAOUT0[127:0] O lbus_clk Receive segmented LBUS data for segment0. The value of the bus is only valid in cycles in which rx_enout0 is sampled as 1.
RX_DATAOUT1[127:0] O lbus_clk Receive segmented LBUS Data for segment1.
RX_DATAOUT2[127:0] O lbus_clk Receive segmented LBUS Data for segment2.
RX_DATAOUT3[127:0] O lbus_clk Receive segmented LBUS Data for segment3.
RX_CHANOUT0[10:0] O lbus_clk Receive channel number for segment0. The bus indicates the channel number of the in-flight packet and is only valid in cycles in which rx_enout0 is sampled as 1.

The maximum number of channels is programmed by the ctl_rx_chan_ext pin. See that pin description for the encoding of that signal.
RX_CHANOUT1[10:0] O lbus_clk Receive channel number for segment1.
RX_CHANOUT2[10:0] O lbus_clk Receive channel number for segment2.
RX_CHANOUT3[10:0] O lbus_clk Receive channel number for segment3.
RX_ENAOUT0 O lbus_clk Receive LBUS enable for segment0. This signal qualifies the other signals of the RX segmented LBUS Interface. Signals for segment0 of the RX LBUS interface are only valid in cycles in which rx_enaout0 is sampled as 1.
RX_ENAOUT1 O lbus_clk Receive LBUS enable for segment1.
RX_ENAOUT2 O lbus_clk Receive LBUS enable for segment2.
RX_ENAOUT3 O lbus_clk Receive LBUS enable for segment3.
RX_SOPOUT0 O lbus_clk Receive LBUS start of packet (SOP) for segment0. This signal indicates the SOP when it is sampled as a 1 and is only valid in cycles in which rx_enaout0 is sampled as a 1.
RX_SOPOUT1 O lbus_clk Receive LBUS SOP for segment1.
RX_SOPOUT2 O lbus_clk Receive LBUS SOP for segment2.
RX_SOPOUT3 O lbus_clk Receive LBUS SOP for segment3.
RX_EOPOUT0 O lbus_clk Receive LBUS EOP for segment0. This signal indicates the end of packet (EOP) when it is sampled as a 1 and is only valid in cycles in which rx_enaout0 is sampled as a 1.
RX_EOPOUT1 O lbus_clk Receive LBUS EOP for segment1.
RX_EOPOUT2 O lbus_clk Receive LBUS EOP for segment2.
RX_EOPOUT3 O lbus_clk Receive LBUS EOP for segment3.
RX_ERROUT0 O lbus_clk Receive LBUS Error for segment0. This signal indicates that the current packet being received has an error when it is sampled as a 1. This signal is only valid in cycles when both rx_enaout0 and rx_eopout0 are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet being received.
RX_ERROUT1 O lbus_clk Receive LBUS Error for segment1.
RX_ERROUT2 O lbus_clk Receive LBUS Error for segment2.
RX_ERROUT3 O lbus_clk Receive LBUS Error for segment3.
RX_MTYOUT0[3:0] O lbus_clk Receive LBUS Empty for segment0. This bus indicates how many bytes of the rx_dataout0 bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both rx_enaout0 and rx_eopout0 are sampled as 1. When rx_errout0 and rx_enaout0 are sampled as 1, the value of rx_mtyout0[2:0] is always 000. Other bits of rx_mtyout0 are as usual.
RX_MTYOUT1[3:0] O lbus_clk Receive LBUS Empty for segment1.
RX_MTYOUT2[3:0] O lbus_clk Receive LBUS Empty for segment2.
RX_MTYOUT3[3:0] O lbus_clk Receive LBUS Empty for segment3.
LBUS Interface – TX Path Signals
TX_RDYOUT O lbus_clk Transmit LBUS Ready. This signal indicates whether the Interlaken core TX path is ready to accept data and provides back-pressure to the user logic. A value of 1 means the user logic can pass data to the core. A value of 0 means the user logic must stop transferring data to the core. When tx_rdyout is asserted depends on a pre-determined value of FIFO fill.
TX_OVFOUT O lbus_clk Transmit LBUS Overflow. This signal indicates whether you have violated the back pressure mechanism provided by the tx_rdyout signal. If tx_ovfout is sampled as a 1, a violation has occurred. You must design the rest of the user logic to prevent the overflow of the TX interface.
TX_DATAIN0[127:0] I lbus_clk Transmit segmented LBUS Data for segment0. This bus receives input data from the user logic. The value of the bus is captured in every cycle that tx_enain0 is sampled as 1.
TX_DATAIN1[127:0] I lbus_clk Transmit segmented LBUS Data for segment1.
TX_DATAIN2[127:0] I lbus_clk Transmit segmented LBUS Data for segment2.
TX_DATAIN3[127:0] I lbus_clk Transmit segmented LBUS Data for segment3.
TX_CHANIN0[10:0] I lbus_clk Transmit LBUS channel number for segment0. This bus receives the channel number for the packet being written. The value of the bus is captured in every cycle that tx_enain0 is sampled as 1.

The maximum number of channels is programmed by the ctl_tx_chan_ext pin. See that pin description for the encoding of that signal.
TX_CHANIN1[10:0] I lbus_clk Transmit LBUS channel number for segment1.
TX_CHANIN2[10:0] I lbus_clk Transmit LBUS channel number for segment2.
TX_CHANIN3[10:0] I lbus_clk Transmit LBUS channel number for segment3.
TX_ENAIN0 I lbus_clk Transmit LBUS enable for segment0. This signal is used to enable the TX LBUS Interface. Signals for segment0 of the TX LBUS interface are sampled only in cycles in which tx_enain0 is sampled as 1
TX_ENAIN1 I lbus_clk Transmit LBUS enable for segment1.
TX_ENAIN2 I lbus_clk Transmit LBUS enable for segment2.
TX_ENAIN3 I lbus_clk Transmit LBUS enable for segment3.
TX_SOPIN0 I lbus_clk Transmit LBUS SOP for segment0. This signal is used to indicate the SOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain0 is sampled as a 1.
TX_SOPIN1 I lbus_clk Transmit LBUS SOP for segment1.
TX_SOPIN2 I lbus_clk Transmit LBUS SOP for segment2.
TX_SOPIN3 I lbus_clk Transmit LBUS SOP for segment3.
TX_EOPIN0 I lbus_clk Transmit LBUS EOP for segment0. This signal is used to indicate the EOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain0 is sampled as a 1.
TX_EOPIN1 I lbus_clk Transmit LBUS EOP for segment1.
TX_EOPIN2 I lbus_clk Transmit LBUS EOP for segment2.
TX_EOPIN3 I lbus_clk Transmit LBUS EOP for segment3.
TX_ERRIN0 I lbus_clk Transmit LBUS Error for segment0. This signal is used to indicate a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain0 and tx_eopin0 are sampled as 1.
TX_ERRIN1 I lbus_clk Transmit LBUS Error for segment1.
TX_ERRIN2 I lbus_clk Transmit LBUS Error for segment2.
TX_ERRIN3 I lbus_clk Transmit LBUS Error for segment3.
TX_MTYIN0[3:0] I lbus_clk Transmit LBUS Empty for segment0. This bus is used to indicate how many bytes of the tx_datain bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that tx_enain0 and tx_eopin0 are sampled as 1. When tx_eopin0 and tx_errin0 are sampled as 1, the value of tx_mtyin0[2:0] is ignored and treated as if it was 000. The other bits of tx_mtyin0 are used as usual.
TX_MTYIN1[3:0] I lbus_clk Transmit LBUS Empty for segment1.
TX_MTYIN2[3:0] I lbus_clk Transmit LBUS Empty for segment2.
TX_MTYIN3[3:0] I lbus_clk Transmit LBUS Empty for segment3.
TX_BCTLIN0 I lbus_clk Transmit force insertion of Burst Control word for segment0. This input is used to force the insertion of a Burst Control Word. When tx_bctlin0 and tx_enain0, are sampled as 1, a Burst Control word is inserted before the data on the tx_datain0 bus is transmitted even if one is not required to observe the BurstMax parameter. This input is used by external schedulers that wish to reduce bandwidth lost due to observation of the BurstShort parameter. (See Use of TX_BCTLIN.) The use of an enhanced scheduling algorithm as described in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008 is required.
TX_BCTLIN1 I lbus_clk Transmit force insertion of Burst Control word for segment1.
TX_BCTLIN2 I lbus_clk Transmit force insertion of Burst Control word for segment2.
TX_BCTLIN3 I lbus_clk Transmit force insertion of Burst Control word for segment3.
LBUS Interface – TX Path Control/Status Signals
CTL_TX_ENABLE I lbus_clk TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only Idle Control Words (and the Meta Frame Words) are transmitted by the Interlaken core. This input should not be set to 1 until the receiver it is sending data to (the receiver in the other device) is fully aligned and ready to receive data. Otherwise, loss of data can occur. This input can be used for Link-Level flow control. For example, setting this input to 0 halts transmission of data and results in the entire link going into XOFF state.
CTL_TX_FC_STAT[255:0] I lbus_clk TX In-Band Flow Control Input. These signals are used to set the status for each calendar position in the in-band-flow control mechanism (see the Interlaken Protocol Definition, Revision 1.2, October 7, 2008). A value of 1 means XON, a value of 0 means XOFF. These bits are transmitted in the Interlaken Control Word bits [55:40].

Each bit of ctl_tx_fc_stat represents an entry in the flow control calendar with a length of 256 entries. When bit 56 of a Control Word is a value of 1, the first 16 calendar entries are output on bits 55-40. Specifically, Bit 55 of the first Control Word reflects the state of ctl_tx_fc_stat[0], bit 54 reflects the state of ctl_tx_fc_stat[1], bit 53 reflects the state of ctl_tx_fc_stat[2], etc. as explained in the example in section 5.3.4.1 of Interlaken spec 1.1. Subsequent Control Words contain the next 16 calendar entries and so forth.

This input must be synchronous with LBUS_CLK.
CTL_TX_MUBITS[7:0] I lbus_clk TX Multiple-Use Control Bits. This bus contains the “Multi-Use” field of the Interlaken Control (see the Interlaken Protocol Definition, Revision 1.2, October 7, 2008). The value of the bus is transmitted in the Interlaken Control Word Bits[31:24]. You must define the function of this bus. If the bus is not used, set all bits to 0.
CTL_TX_RLIM_ENABLE I lbus_clk TX Rate Limiter Enable. This signal is used to enable the Rate Limiter. A value of 1 turns on the Rate Limiter and a value of 0 turns off the Rate Limiter.
CTL_TX_RLIM_MAX[11:0] I lbus_clk TX Rate Limiter Maximum Token Count. This bus is used to set the maximum number of tokens in the bucket.

A token is equal to 1 byte.
CTL_TX_RLIM_DELTA[11:0] I lbus_clk TX Rate Limiter Delta. This bus is used to set the number of tokens to add to the bucket each interval.

A token is equal to 1 byte.
CTL_TX_RLIM_INTV[7:0] I lbus_clk TX Rate Limiter Update Interval. This bus is used to set the number of LBUS clock cycles between additions of ctl_tx_rlim_delta tokens to the bucket.
CTL_TX_DIAGWORD_LANESTAT[11:0] I Async Lane Status messaging inputs. This bus sets bit 33 in the Diagnostic Word for the respective lane. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
CTL_TX_DIAGWORD_INTFSTAT I Async Interface Status messaging inputs. This signal sets bit 32 in the Diagnostic Word of each lane. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
STAT_TX_UNDERFLOW_ERR O lbus_clk TX Underflow. This signal indicates if the LBUS interface is being clocked too slowly to properly fill the link with data.

In normal operation, this signal is always sampled as 0.

If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
STAT_TX_OVERFLOW_ERR O lbus_clk TX Overflow. This output should never be asserted and indicates a critical failure. The core needs to be reset.

This output is synchronous with the LBUS_CLK.
STAT_TX_BURST_ERR O lbus_clk TX BurstShort Error. When this signal is a value of 1, a burst (that is, a sequence of Data Words between two Control Words) was shorter than the value specified by ctl_tx_burstshort. This signal is only asserted if the final Control Word did not contain an EOP. This signal is provided to identify a poor scheduler design that results in reduced LBUS transaction errors. The TX core must be reset if this signal is asserted.
LBUS Interface – RX Path Control/Status Signals
CTL_RX_FORCE_RESYNC I Async RX Resync input. This signal is used to force the RX lane logic to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation.

This input should normally be Low and should only be pulsed (1 cycle minimum pulse) to force realignment.

Note: CTL_RX_FORCE_RESYNC restarts the synchronization state machine but doesn’t reset the GT logic. In most cases when there is an RX failure, the GT RX need to be reset.
STAT_RX_BURSTMAX_ERR O lbus_clk RX BurstMax Error. When this signal is a value of 1, a burst (that is, a sequence of Data Words between two Control Words) was detected that was longer than the value of BurstMax specified by ctl_rx_burstmax. This signal is informational only and can be optionally ignored.
STAT_RX_DIAGWORD_LANESTAT[11:0] O lbus_clk Lane Status messaging outputs. This bus reflects the most recent value in bit 33 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in stat_rx_crc32_valid is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
STAT_RX_DIAGWORD_INTFSTAT[11:0] O lbus_clk Lane Status messaging outputs. This bus reflects the most recent value in bit 32 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in stat_rx_crc32_valid is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
STAT_RX_CRC32_VALID[11:0] O lbus_clk Diagnostic Word CRC32 Valid. This bus reflects the validity of the CRC32 in the most recently received Diagnostic Word for the respective lane. A value of 1 indicated the CRC32 was valid and a value of 0 indicated the CRC32 was invalid. See section 5.4.6 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
STAT_RX_CRC32_ERR[11:0] O lbus_clk Diagnostic Word CRC32 Error/Invalid. This bus provides indication of an invalid CRC32 in the Diagnostic Word for the respective lane. These signals are asserted with a value of 1 for one LBUS clock cycle each time an error is detected.
STAT_RX_FC_STAT[255:0] O lbus_clk RX Flow control Outputs. These signals indicate the flow control status for all of the calendar positions of the received data. A value of 1 means XON, a value of 0 means XOFF.

These outputs reflect the information contained in bits 55-40 of the Control Words received by the RX. Only 256 In-Band flow control bits are supported. If a longer calendar is received, latter bits are ignored and are never output. If a shorter calendar is received, the bits of stat_rx_fc_stat that were not updated maintain their previous state. Each bit of stat_rx_fc_stat represents a received flow control calendar entry. Stat_rx_fc_stat[0] is the first received calendar entry, stat_rx_fc_stat[1] is the second received calendar entry, stat_rx_fc_stat[2] is the third received calendar entry, etc. as explained in the example in section 5.3.4.1 in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008. Whenever a CRC24 or a loss of lane alignment occurs, all bits of stat_rx_fc_stat are set to a value of 0.

This output is synchronous with the LBUS_CLK.
STAT_RX_MUBITS[7:0] O lbus_clk:

if retransmission is disabled.

core_clk:

if retransmission is enabled.

 RX Multiple-Use Control Bits. This bus contains the “Multi-Use” field of the Interlaken Control (see the Interlaken Protocol Definition, Revision 1.2, October 7, 2008). The value of the bus are Bits[31:24] of the most recently received Interlaken Control Word.
STAT_RX_SYNCED[11:0] O lbus_clk Word Boundary Synchronized. These signals indicate whether a lane is word boundary synchronized. A value of 1 indicates the corresponding lane has achieved word boundary synchronization as follows:
  1. 64B/67B Word Boundary Locked
  2. Correctly receiving the Meta Frame Synchronization Word, and
  3. Correctly receiving the Scrambler State Control Word as described in sections 5.4.2, 5.4.3, and 5.4.4 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.

This output is synchronous with LBUS_CLK.
STAT_RX_SYNCED_ERR[11:0] O lbus_clk Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective lane. A value of 1 indicates the corresponding lane had a word boundary synchronization error.
STAT_RX_MF_LEN_ERR[11:0] O lbus_clk Meta Frame Length Error. These signals indicate whether a Meta Frame length mismatch occurred in the respective lane. A value of 1 indicates the corresponding lane is receiving Meta Frame of wrong length.
STAT_RX_MF_REPEAT_ERR[11:0] O lbus_clk Meta Frame Consecutive Error. These signals indicate whether consecutive Meta Frame errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane.
STAT_RX_DESCRAM_ERR[11:0] O lbus_clk Scrambler State Control Word Error. These signals indicate a mismatch between the received Scrambler State Word and the expected value. A value of 1 indicates an error in the corresponding lane.
STAT_RX_ALIGNED O lbus_clk All Lanes Aligned/Deskewed. This signal indicates whether or not all lanes are aligned and deskewed. A value of 1 indicates all lanes are aligned and deskewed.

When this signal is a 1, the RX path is aligned and can receive packet data.
STAT_RX_ALIGNED_ERR O lbus_clk Loss of Lane Alignment/Deskew. This signal indicates an error occurred during lane alignment or lane alignment was lost. A value of 1 indicates an error occurred.
STAT_RX_CRC24_ERR O lbus_clk Control Word CRC24 Error. This signal indicates whether or not a mismatch occurred between the received and the expected CRC24 value. A value of 1 indicates a mismatch occurred.
STAT_RX_OVERFLOW_ERR O lbus_clk RX FIFO Overflow Error. This signal indicates if the LBUS interface is being clocked too slowly to properly receive the data being transmitted across the link. A value of 1 indicates an error occurred.

In normal operation, this signal is always sampled as 0.

If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
STAT_RX_MF_ERR[11:0] O lbus_clk Meta Frame Synchronization Word Error. These signals indicate that an incorrectly formed Meta Frame Synchronization Word was detected in the respective lane. A value of 1 indicates an error occurred.
STAT_RX_FRAMING_ERR[11:0] O lbus_clk Framing Error. These signals indicate that an illegal framing pattern was detected in the respective lane. A value of 1 indicates an error occurred.
STAT_RX_MSOP_ERR O lbus_clk Missing SOP Error. This signal indicates that a Missing SOP was detected (and corrected).
STAT_RX_MEOP_ERR O lbus_clk Missing EOP Error. This signal indicates that a Missing EOP was detected (and corrected).
STAT_RX_BURST_ERR O lbus_clk Burst Error. This signal indicates that a BurstShort or a burst length error was detected.
STAT_RX_MISALIGNED O lbus_clk Alignment Error. This signal indicates that the lane aligner did not receive the expected Meta Frame Synchronization Word across all (active) lanes. This signal can be used to collect the statistic "RX_Alignment_Error" as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008. This signal is not asserted until the Meta Frame Synchronization Word has been received at least once across all lanes. A value of 1 indicates the error occurred.
STAT_RX_BAD_TYPE_ERR[11:0] O lbus_clk Unexpected or Illegal Meta Frame Control Word Block Type. These signals indicate an unexpected or illegal Meta Frame Control Word Block Type was detected. These signals can be used to collect the statistic "RX_Bad_Control_Error" as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008. A value of 1 indicates an error in the corresponding lane.
STAT_RX_MUBITS_UPDATED O lbus_clk:

if retransmission is disabled.

core_clk:

if retransmission is enabled.

 RX Multiple-Use/General Purpose Control Bits Updated. This output indicates that STAT_RX_MUBITS has been updated and is asserted for one clock cycle.
STAT_RX_WORD_SYNC[11:0] O lbus_clk 64B/67B Word Boundary Locked. These signals indicate whether a lane is 64B/67B word boundary locked. A 64B/67B word boundary lock occurs if a lane detects 64 consecutive valid framing patterns on Bits[65:64] as per the Interlaken Protocol Definition, Revision 1.2, October 7, 2008 Section 5.4.2. These signals are independent of both the Meta Frame Synchronization Word and Scrambler State Control Word. A value of 1 indicates the corresponding lane has achieved 64B/67B word boundary lock.
Protocol Bypass (Lane Logic Only) Interface – RX Path Signals
RX_BYPASS_RDIN I core_clk This signal initiates a read operation.
RX_BYPASS_FORCE_REALIGNIN I core_clk This signal causes the word synchronizer to sync again.
RX_BYPASS_IS_AVAILOUT[11:0] O core_clk This signal indicates whether the data can be read using the rx_bypass_rdin signal.
RX_BYPASS_DATAOUT0[65:0] O core_clk Data or control word output for bypass lane0.
RX_BYPASS_DATAOUT1[65:0] O core_clk Data or control word output for bypass lane1.
RX_BYPASS_DATAOUT2[65:0] O core_clk Data or control word output for bypass lane2.
RX_BYPASS_DATAOUT3[65:0] O core_clk Data or control word output for bypass lane3.
RX_BYPASS_DATAOUT4[65:0] O core_clk Data or control word output for bypass lane4.
RX_BYPASS_DATAOUT5[65:0] O core_clk Data or control word output for bypass lane5.
RX_BYPASS_DATAOUT6[65:0] O core_clk Data or control word output for bypass lane6.
RX_BYPASS_DATAOUT7[65:0] O core_clk Data or control word output for bypass lane7.
RX_BYPASS_DATAOUT8[65:0] O core_clk Data or control word output for bypass lane8.
RX_BYPASS_DATAOUT9[65:0] O core_clk Data or control word output for bypass lane9.
RX_BYPASS_DATAOUT10[65:0] O core_clk Data or control word output for bypass lane10.
RX_BYPASS_DATAOUT11[65:0] O core_clk Data or control word output for bypass lane11.
RX_BYPASS_ENAOUT[11:0] O core_clk This signal qualifies the corresponding rx_bypass_dataout bus.
RX_BYPASS_IS_BADLYFRAMEDOUT[11:0] O core_clk This signal identifies the metaframe words that must be discarded for each lane.
RX_BYPASS_IS_SYNCWORDOUT[11:0] O core_clk This signal identifies metaframe synchronization words.
RX_BYPASS_IS_OVERFLOWOUT[11:0] O core_clk This signal indicates whether the lane buffer has overflowed.
RX_BYPASS_IS_SYNCEDOUT[11:0] O core_clk This signal indicates that the corresponding lane is synced to metaframe and is ready for alignment.
Protocol Bypass (Lane Logic Only) Interface – TX Path Signals
TX_BYPASS_ENAIN I tx_serdes_refclk This signal qualifies the TX inputs.
TX_BYPASS_GEARBOX_SEQIN[7:0] I tx_serdes_refclk This signal determines the gearbox sequencing according to a pre-determined format.
TX_BYPASS_MFRAMER_STATEIN[3:0] I tx_serdes_refclk This signal determines the metaframe state according to a pre-determined format.
TX_BYPASS_CTRLIN[11:0] I tx_serdes_refclk This signal identifies a word as being either data or control for the corresponding lane.
TX_BYPASS_DATAIN0[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane0.
TX_BYPASS_DATAIN1[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane1.
TX_BYPASS_DATAIN2[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane2.
TX_BYPASS_DATAIN3[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane3.
TX_BYPASS_DATAIN4[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane4.
TX_BYPASS_DATAIN5[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane5.
TX_BYPASS_DATAIN6[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane6.
TX_BYPASS_DATAIN7[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane7.
TX_BYPASS_DATAIN8[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane8.
TX_BYPASS_DATAIN9[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane9.
TX_BYPASS_DATAIN10[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane10.
TX_BYPASS_DATAIN11[63:0] I tx_serdes_refclk This bus is the data (or control) words for lane11.
Retransmission Interface
CTL_TX_RETRANS_ENABLE I Static TX Retransmission Enable. This signal enables the retransmission feature for the Transmit path. When this input is a value of 1, the input CTL_TX_MUBITS is ignored. This input is static and only changed during reset.
CTL_TX_ERRINJ_BITERR_GO I lbus_clk When this input is assigned a value of 1 for a single Local bus clock cycle, it initiates the generation of a single bit error. The error will occur on the selected lane only once.

Once CTL_TX_ERRINJ_BITERR_GO has been assigned a value of 1 for a single Local bus clock cycle, it should not be assigned a value of 1 again until STAT_TX_ERRINJ_BITERR_DONE has changed from a value of 1 to a value of 0 to a value of 1 again.
STAT_TX_ERRINJ_BITERR_DONE O lbus_clk Initially this output has a value of 1 to indicate that the error injector is ready to inject a new error. After

CTL_TX_ERRINJ_BITERR_GO is asserted, this signal is negated and attains a value of 0. When all of the errors have been injected, this output attains a value of 1 again.
CTL_TX_ERRINJ_BITERR_LANE[3:0] I lbus_clk This input is used to select which lane the error will be injected on. A valid, commissioned lane must be selected.

This input is pseudo-static and should only be changed when CTL_TX_ERRINJ_BITERR_GO has a value of 0 and STAT_TX_ERRINJ_BITERR_DONE has a value of 1.
CTL_TX_RETRANS_REQ I lbus_clk Request Input. This input is used to request retransmission and is ignored if:
  • CTL_TX_RETRANS_ENABLE has a value of 0
  • CTL_TX_RETRANS_REQ_VALID has a value of 0
  • There is insufficient data written into the buffer

Also, in order for a request for retransmission to be accepted, a clock cycle with CTL_TX_RETRANS_REQ_VALID set to a value of 1 with a request set to a value of 0 must occur before a clock cycle

with CTL_TX_RETRANS_REQ_VALID set to a value of 1 with request set to a value of 1. This is in keeping with the requirement in section 2.2.1 of the Interlaken Retransmit Extension Protocol Definition, Revision 1.2, June 28, 2012 which states: "The bit in the calendar must be deasserted, set to Xoff, before another retransmit request can be signaled."

This input is intended to be connected to one of the rx_fc bits on the RX Out-of-Band flow control interface.

CTL_TX_RETRANS_REQ_VALID I lbus_clk Request Valid Input. This input is used to qualify the input request as described previously. This input is intended to be connected to the rx_update bit that corresponds to the selected rx_fc bit on the RX Out-of-Band flow control interface.
STAT_TX_RETRANS_RAM_WDATA[644-1:0] O lbus_clk TX Retransmission buffer write data
STAT_TX_RETRANS_RAM_WE_B0 O lbus_clk TX Retransmission buffer write enable for RAM Bank 0
STAT_TX_RETRANS_RAM_WE_B1 O lbus_clk TX Retransmission buffer write enable for RAM Bank 1
STAT_TX_RETRANS_RAM_WE_B2 O lbus_clk TX Retransmission buffer write enable for RAM Bank 2
STAT_TX_RETRANS_RAM_WE_B3 O lbus_clk TX Retransmission buffer write enable for RAM Bank 3
STAT_TX_RETRANS_RAM_WADDR[9-1:0] O lbus_clk TX Retransmission buffer write address
CTL_TX_RETRANS_RAM_RDATA[644-1:0] I lbus_clk TX Retransmission buffer read data
STAT_TX_RETRANS_RAM_RD_B0 O lbus_clk TX Retransmission buffer read enable for RAM Bank 0
STAT_TX_RETRANS_RAM_RD_B1 O lbus_clk TX Retransmission buffer read enable for RAM Bank 1
STAT_TX_RETRANS_RAM_RD_B2 O lbus_clk TX Retransmission buffer read enable for RAM Bank 2
STAT_TX_RETRANS_RAM_RD_B3 O lbus_clk TX Retransmission buffer read enable for RAM Bank 3
STAT_TX_RETRANS_RAM_RADDR[9-1:0] O lbus_clk TX Retransmission buffer read address
STAT_TX_RETRANS_RAM_RSEL[1:0] O lbus_clk TX Retransmission Read Data Select. This input is used to select the read data from the corresponding RAM bank and latch the data into CTL_RX_RETRANS_RAM_RDATA. This signal is valid two clock cycles after the read signal of the corresponding RAM bank is asserted. The following values are defined:
  • 00 = Select read data from RAM Bank 0
  • 01 = Select read data from RAM Bank 1
  • 10 = Select read data from RAM Bank 2
  • 11 = Select read data from RAM Bank 3
CTL_TX_RETRANS_RAM_PERRIN I lbus_clk Retransmission read data parity error input.

This input is for external parity logic that checks the validity of data read from the retransmission buffer. When this input has a value of 1, it causes the forwarding of data to halt, and causes the STAT_TX_RETRANS_RAM_PERROUT signal to be asserted. When this input is unused, it must be tied to a value of 0.
STAT_TX_RETRANS_BURST_ERR O lbus_clk TX Retransmission BurstShort error.

This output is asserted with a value of 1 if a burst, less than BurstShort, not ending with an EOP, is written into the TX when CTL_TX_RETRANS_ENABLE has a value of 1.
STAT_TX_RETRANS_BUSY O lbus_clk TX Retransmission Buffer Busy. When this output has a value of 1, it indicates the buffer is retransmitting data.
STAT_TX_RETRANS_RAM_PERROUT O lbus_clk Retransmission read data parity error output.

This output is asserted whenever CTL_TX_RETRANS_RAM_PERRIN is asserted and indicates that a fatal error has occurred and the TX path has been halted. A reset is required to clear this signal.
CTL_RX_RETRANS_ENABLE I Static RX Retransmission Enable.

This signal enables the retransmission feature for the Receive path when asserted. This input should be static and only changed during reset.
STAT_RX_RETRANS_REQ O lbus_clk Interlaken RX Retransmission Request. When enabled, this output requests an external TX to retransmit recent bursts because a burst sequence error of some sort was detected. This output changes from 0 to a value of 1 and remains at 1 while the input CTL_RX_RETRANS_ACK has a value of 0. If CTL_RX_RETRANS_ACK is tied to a value of 1, this output will only be a value of 1 for a single LBUS cycle.
CTL_RX_RETRANS_ACK I lbus_clk Interlaken RX Retransmission Acknowledge. This input is used to clear the signal stat_rx_retrans_req. When both ctl_rx_retrans_ack and stat_rx_retrans_req have a value of 1, the output stat_rx_retrans_req is forced to a value of 0.
STAT_RX_RETRANS_STATE[2:0] O core_clk Interlaken RX Retransmission State. These outputs indicate the state of the RX Retransmission logic:
  • 000 = waiting for initial bursts
  • 001 = normal operating mode
  • 010 = an error was detected and the short timer is counting
  • 011 = waiting for a discontinuity
  • 100 = waiting for a new sequence
  • 101 = waiting for the expected sequence
  • 110 = error detected and waiting for assertion of CTL_RX_RETRANS_RESET
  • 111 = waiting for negation of CTL_RX_RETRANS_RESET
STAT_RX_RETRANS_SEQ[7:0] O core_clk Interlaken RX Retransmission Primary Sequence Number. When CTL_RX_RETRANS_ENABLE has a value of 1, these outputs indicate the value of Bits[31:24] of the Burst Control Word most recently forwarded to the LBUS interface.
STAT_RX_RETRANS_SUBSEQ[4:0] O core_clk Interlaken RX Retransmission Sub-Sequence Number. When CTL_RX_RETRANS_ENABLE has a value of 1, these outputs indicate the implied sub-sequence of the Burst Control Word most recently forwarded to the LBUS interface.
Note: The values of these bits might not be correct when STAT_RX_RETRANS_STATE = 000.
STAT_RX_RETRANS_SEQ_UPDATED O core_clk Interlaken RX Retransmission Sequence Number Updated. When CTL_RX_RETRANS_ENABLE has a value of 1, this output indicates that STAT_RX_RETRANS_SEQ has been updated and is asserted for one clock cycle.
CTL_RX_RETRANS_RESET I lbus_clk Interlaken RX Retransmission Reset. When this input has a value of 1, the RX retransmission logic is reset. This is not a general purpose input but only has an effect if a fatal retransmission error has been detected.
CTL_RX_RETRANS_RESET_MODE I lbus_clk Interlaken RX Retransmission Reset Mode. This input only has an effect with the negation of CTL_RX_RETRANS_RESET. If this input has a value of 0, with the negation CTL_RX_RETRANS_RESET, the RX will mark open packets as having an error and wait for the expected sequence. If this input has a value of 1, with the negation CTL_RX_RETRANS_RESET, the RX will mark open packets as having an error and establish a new sequence.
STAT_RX_RETRANS_RETRY_ERR O core_clk Interlaken RX Retransmission Retry Error. This output indicates too many re-requests for a particular sequence that occurred as defined by CTL_RX_RETRANS_RETRY. This output changes from a value of 0 to a value of 1 when the fatal error condition is detected and remains asserted until the input CTL_RX_RETRANS_RESET is asserted and negated.
STAT_RX_RETRANS_WRAP_ERR O core_clk Interlaken RX Retransmission Wrap Around Error. This output indicates that after a request for retransmission was made, the expected sequence arrived but was preceded by too many other bursts suggesting that the "true" burst to be received was lost. This output changes from a value of 0 to a value of 1 when the error condition is detected and remains asserted until the input CTL_RX_RETRANS_RESET is asserted and negated.
STAT_RX_RETRANS_WDOG_ERR O core_clk Interlaken RX Retransmission Watchdog Timer Error. This output indicates the counter associated with CTL_RX_RETRANS_WDOG has reached its maximum value. This output changes from a value of 0 to a value of 1 when the fatal error condition is detected and remains asserted until the input CTL_RX_RETRANS_RESET is asserted and negated.
CTL_RX_RETRANS_ERRIN I lbus_clk Interlaken RX Retransmission Forced Error. This input is used to force a fatal error. When asserted, the input CTL_RX_RETRANS_RESET must be asserted and negated. If unused, this input must be tied to a value of 0.
STAT_RX_RETRANS_DISC O core_clk Interlaken RX Retransmission Discontinuity. When CTL_RX_RETRANS_ENABLE has a value of 1, this output indicates that a discontinuity was detected.
STAT_RX_RETRANS_CRC24_ERR O core_clk Interlaken RX Retransmission CRC24 Error. When CTL_RX_RETRANS_ENABLE has a value of 1, this output indicates that a CRC24 error was detected.
CTL_RX_RETRANS_FORCE_REQ I lbus_clk Interlaken RX Retransmission Forced Request. This input is used to force a request for retransmission and only does two things:
  • Asserts STAT_RX_RETRANS_REQ
  • Clears the timer associated with STAT_RX_RETRANS_LATENC

This input should only be asserted for one clock cycle.
STAT_RX_RETRANS_LATENCY[15:0] O lbus_clk Interlaken RX Retransmission Request to Discontinuity Latency. This timer is used to measure the latency from request for retransmission to the receipt of the associated discontinuity in terms of Interlaken Words. When STAT_RX_RETRANS_REQ is asserted, STAT_RX_RETRANS_LATENCY is set to 0. When the next discontinuity is received, STAT_RX_RETRANS_LATENCY is updated with the number of Interlaken Words that have been received. If no discontinuity is received, STAT_RX_RETRANS_LATENCY is set to 'hFFFF.
DRP Path/Control Signals
DRP_DO[15:0] O DRP_CLK Data bus for reading configuration data from the ILKN to the FPGA logic resources.
DRP_RDY O DRP_CLK Indicates operation is complete for write operations and data is valid for read operations.
DRP_ADDR[9:0] I DRP_CLK DRP Address Bus.
DRP_CLK I DRP Interface Clock. When DRP is not used, this can be tied to GND.
DRP_DI[15:0] I DRP_CLK Data bus for writing configuration data from the FPGA logic resources to the Interlaken core.
DRP_EN I DRP_CLK DRP Enable Signal.
  • 0: No read or write operations performed.
  • 1: Enables a read or write operation.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.
DRP_WE I DRP_CLK DRP Write Enable.
  • 0: Read operation when DRP_EN is 1.
  • 1: Write operation when DRP_EN is 1.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.