Packet Generation - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)

Document ID
PG169
Release Date
2024-06-05
Version
2.4 English

As mentioned earlier interlaken_0_pkt_gen is responsible for the generation of packets. Typically packet generator waits for the GT to get locked and Interlaken RX to get aligned. After alignment, the packet generator generates a predefined number of packets. The finite state machine (FSM) description of each state follows, and the state transition that occurs during this process is shown in the following figure.

TOP_IDLE_STATE
By default the controller will be in this state. When reset_done signal becomes active-High, it moves to GT_LOCK_STATE.
GT_LOCK_STATE
Sets the following:
  • ctl_tx_enable = 1’b0
  • ctl_tx_mubits = 8’d0
  • ctl_tx_diagword_lanestat = 12'hFFF
  • ctl_tx_diagword_intfstat = 1'b1
  • init_done = 1'b0
and moves to WAIT_RX_ALIGN_STATE.
WAIT_RX_ALIGN_STATE
Waits for the Interlaken core stat_rx_aligned or simplex_mode_rx_aligned in simplex TX mode, which indicates that the ILKN RX core is aligned. After that, FSM moves to ENABLE_PKT_TRANS_STATE state.
ENABLE_PKT_TRANS_STATE
Sets the ctl_tx_enable = 1’b1 and moves to PKT_TX_INIT_STATE.
PKT_TX_INIT_STATE
Initialize all signals to start LBUS packet generation. When init_done and tx_rdyout is set, move to TRANSMIT_STATE_0.
TRANSMIT_STATE_0
Checks for the number of packets to be generated, and generates predefined size of LBUS packets.
  • Moves to TRANSMIT_STATE_1 after sending respective SOP and EOP, and other LBUS control signals using the send_packet function.
  • After sending all the packets, the FSM moves to the DONE_STATE.
  • During transmission of the packets if ready = 0, the FSM controller moves to HOLD_STATE.
TRANSMIT_STATE_1
Sends remaining LBUS packet.
  • Once pkt_end reached, FSM moves to TRANSMIT_STATE_0 to end the current LBUS packet and start new packet.
  • During transmission of the packets if ready = 0, FSM controller moves to HOLD_STATE.
DONE_STATE
Sets tx_done_int = 1’b1 and moves to PKT_RESTART_STATE.
HOLD_STATE
If ready = 1, the FSM controller moves to TRANSMIT_STATE_0 or TRANSMIT_STATE_1 depending on which state it came from.
PKT_RESTART_STATE
Sets gen_busy = 0 and moves to TOP_IDLE_STATE.
Figure 1. State Transition Diagram for Packet Generator

In the Simple TX mode of operation because RX alignment information is not available, the state machine waits for you to input simplex_mode_rx_aligned. After you assert this input, the packet transmission starts.