This is the mode of operation if CTL_RX_RETRANS_TIMER1 is set to a
non-zero value and CTL_RX_RETRANS_TIMER2 is set to a value of zero.
In this mode, while timer1 is counting, all CRC24 errors are ignored but valid sequence discontinuities are handled. This mode of operation is simpler because a valid sequence discontinuity is unambiguous and never contains any "short term secondary errors."
In this mode, CTL_RX_RETRANS_TIMER1 should be set to a value greater
than the maximum request-to-discontinuity latency and
CTL_RX_RETRANS_TIMER2 to a value of zero.
Note:
AMD strongly recommends configuring the
timers in Mode 2.