Measuring Request-to-Discontinuity Latency - Measuring Request-to-Discontinuity Latency - 2.4 English - PG169

In order for the retransmission logic in the RX to operate correctly, the inputs CTL_RX_RETRANS_TIMER1 and CTL_RX_RETRANS_TIMER2 must be configured with suitable values based on the maximum request-to-discontinuity latency.

Each time the RX makes a request for retransmission, a counter begins counting from 0 and continues until a sequence discontinuity is detected or the counter reaches its limit. The result of this counter is available on the port STAT_RX_RETRANS_LATENCY[15:0].

A request for retransmission can be forced by asserting the input CTL_RX_RETRANS_FORCE_REQ for a single clock cycle.

To measure the request-to-discontinuity latency, the TX core must be configured appropriately. Some RAM needs to be available for buffering and CTL_TX_RETRANS_ENABLE must be a value of 1. The TX must respond to CTL_TX_RETRANS_REQ with the assertion of STAT_TX_RETRANS_BUSY. It is not necessary to have the correct amount of RAM to determine the latency. All that has to happen is that the TX core generate a discontinuity in response to a request for retransmission.

The timers CTL_RX_RETRANS_TIMER1 and CTL_RX_RETRANS_TIMER2 need not be set to determine the latency. A retransmission multiplier of 16 or 32 can be chosen. When the latency is determined, these values and the TX buffer depth can be adjusted.

The request-to-discontinuity latency can be measured using the following technique:

1. A retransmission capable TX continually sends packets.
2. CTL_RX_RETRANS_RETRY is initialized to a value of 0.
3. Assign CTL_RX_RETRANS_RESET_MODE a value of 0.
4. Wait until STAT_RX_RETRANS_STATE equals 3'b001.
5. Assert CTL_RX_RETRANS_FORCE_REQ for a single clock cycle.
6. Wait for STAT_RX_RETRANS_RETRY_ERR to be asserted.
7. Assert CTL_RX_RETRANS_RESET for a single clock cycle.
8. Read the resulting value from STAT_RX_RETRANS_LATENCY.
9. Assign CTL_RX_RETRANS_RESET_MODE a value of 1.
10. Assert CTL_RX_RETRANS_ERRIN for a single clock cycle.
11. Assert CTL_RX_RETRANS_RESET for a single clock cycle.

When STAT_RX_RETRANS_RETRY_ERR is asserted, STAT_RX_RETRANS_STATE should equal 3'b110 and STAT_RX_RETRANS_LATENCY should be cleared to a value of 16'h0000. With CTL_RX_RETRANS_RESET_MODE equal to 0, asserting CTL_RX_RETRANS_RESET a single cycle should cause STAT_RX_RETRANS_STATE to change to 3'b111 and then to 3'b100 and STAT_RX_RETRANS_LATENCY should be updated with the measured latency. When the latency is read, asserting CTL_RX_RETRANS_ERRIN should cause STAT_RX_RETRANS_STATE to change to 3'b110. With CTL_RX_RETRANS_RESET_MODE equal to 1, asserting CTL_RX_RETRANS_RESET a single cycle should cause STAT_RX_RETRANS_STATE to change to 3'b111 and then to 3'b000.

The resulting value of STAT_RX_RETRANS_LATENCY is the number of Interlaken Words received during the interval between the request for retransmission and the receipt of a valid sequence discontinuity or in other words, the request-to-discontinuity latency. The process should be repeated several times and the maximum value recorded to configure the timers.