Invalid Cycles - 2.4 English - PG169

The following table shows several invalid TX segmented LBUS cycles as indicated by the asterisks. In these examples, BurstMax has been set to 256 and BurstShort to 64.

Figure 1. Invalid Segmented LBUS Cycles

• Cycle 3 is not valid because it contains two SOPs.
• Cycle 5 does not contain an EOP even though there is an SOP in the next cycle.
  Note: In Burst Interleaved mode, this is permitted because the current packet ends in a later cycle.
• Cycle 6 has an SOP even though the preceding packet was not closed with an EOP. This sequence is not permitted by the LBUS rules and results in undefined behavior.
• Cycle 7 contains idles even though there is no EOP or BurstMax.
• Cycle 9 contains an idle segment during a packet transfer which is not permitted by the segmented LBUS rules.
• Cycle 18 is not permitted because a data transfer is being performed even though tx_rdyout has been deasserted for eight consecutive cycle.
• Cycle 19 must never be performed because tx_ovfout has been asserted. In the event of tx_ovfout being asserted, the TX should be reset.