The AMD Integrated Interlaken LogiCORE IP is a scalable chip-to-chip interconnect protocol designed to enable the following for use in select AMD UltraScale™ and AMD UltraScale+™ architectures:
- The protocol logic supported in each integrated IP core scales up to 150 Gb/s.
- The protocol bypass (lane logic only) mode allows for 1-12 lanes up to 12.5G on UltraScale and up to 25.78125 Gb/s on UltraScale+ architecture on each serial transceiver to be used to build a fully featured Interlaken interface.
The Integrated Interlaken IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008. This integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 40 to 50k logic cells (LCs) per instantiation and uses about 1/8th the power of soft implementations.