The following figure shows the GT selection and configuration options for the IP.
Figure 1. GT Selections and Configuration Tab
The following table describes the options available in the ILKN/GT Selection and Configuration tab.
| Parameter | Description | Default Value | Value Range |
|---|---|---|---|
| GT Location | |||
| GT Location | Select whether the GT IP is included in the core or in the example design. | Include GT subcore in core | Include GT subcore in example design |
| Interlaken Lane to Transceiver Association | |||
| ILKN Core Selection | XY location of the transceiver connected to the Interlaken core | Based on the selected package/device | Options based on the selected package/device |
| GT Group Selection | Based on the FPGA, part number, GT type selected, and number of lanes, the available ILKN cores for the particular device/package. The best and all possible GT groups are listed as per GT selection guidelines | Based on device, package and core location, the best possible GT combinations are listed | Possible combination based on the device, package, and core location selected |
| Lane 00 to Lane 11 | Lanes will be auto filled, based on the selection of the ILKN core location and GT group selection. | Auto filled | |
| Shared Logic | |||
| Include Shared Logic In | Determines the location of the transceiver shared logic | Core | Core Example Design |
| Advanced Options | |||
| Receiver | |||
| RX Insertion Loss at Nyquist (dB) | Specify the insertion loss of the channel between the transmitter and receiver at the Nyquist frequency in dB | 10 | Depends on GT |
| RX Equalization Mode | When Auto is specified, the equalization mode implemented by the Wizard depends on the value specified for insertion loss at Nyquist. Refer to UltraScale Architecture GTH Transceivers User Guide (UG576) to determine the appropriate equalization mode for your system. | Auto | Auto DFE LPM |
| GT QPLL | |||
| PLL Type | GT PLL Type | QPLL0 | QPLL0 QPLL1 |
| Others | |||
| Enable Pipeline Registers | Selecting this option will include one stage pipeline register between ILKN core and the GT to ease timing | 0 | 0 – Disable 1 – Enable |
| Enable Additional GT Control/Status and DRP Ports | If selected, enables additional GT control, status, and DRP ports | 0 | 0 – Disable 1 – Enable |