- Programmable BurstMax, BurstShort, and MetaFrameSize parameters
- 64B/67B encoding and decoding
- Automatic word and lane alignment
- Synchronous data scrambler
- Uses GTY or GTH transceivers for UltraScale+ and UltraScale devices
- 512-bit segmented LBUS user-side interface
- 64-bit interface to the serial transceiver
- CRC24 generation and checking for burst data integrity
- CRC32 generation and checking for lane data integrity
- Programmable rate limiting circuitry
- Rate matching with a granularity of 1 Gb/s
- Robust error condition detection and recovery
- Channel-level and link-level flow control mechanism
- Support for up to 2,048 different logical channels
- BurstMax can be programmed up to 256 bytes
- Support for BurstShort minimum of 64 bytes and subsequent increments of 32 bytes
- Support for up to 256 different In-Band flow control channels and 2048 out-of-band flow control channels
- Support for link-level flow control
- Meta frame length programmable between 128 to 8K words
- Support for status messaging
- Dynamic reconfiguration port (DRP) interface for dynamic reconfiguration of the core
- Protocol bypass (lane logic only) mode. See IP Facts.