The figure shows the instantiation of various modules and their hierarchy in the example design when the GT (serial transceiver) is outside the IP core, that is, in the example design. This hierarchical example design is delivered when you select the Include GT subcore in example design option from the ILKN/GT Selection and Configuration tab.
The Interlaken_0_core_support.v is present in the hierarchy when you select the Include GT subcore in example design option from the ILKN/GT Selection and Configuration tab or the Include Shared Logic in example design option from the ILKN/GT Selection and Configuration tab.
This instantiates the Interlaken_0_shared_logic_wrapper.v module and the Interlaken_0.v module for the Include Shared Logic in example design option. The Interlaken_0_gt_wrapper.v module will be present when you select the GT subcore in example design option.
The Interlaken_0 module instantiates the Interlaken_0_wrapper module that has the Interlaken and Sync registers along with the pipeline registers to synchronize the data between the Interlaken core and the GT subcore (in the example design). The GT subcore generates the required clock frequencies with help of the clocking helper blocks for the Interlaken core. The Interlaken_0_pkt_gen_mon module instantiates the Interlaken_0_pkt_gen (packet generator) and Interlaken_0_pkt_mon (packet monitor). The Interlaken_0_pkt_gen_mon and Interlaken_0 handshake with each other using a few signals such as GT locked, RX alignment, and data transfer signals as per the LBUS protocol (more on this will be described in later sections). The Interlaken_0_pkt_gen module is mainly responsible for the generation of packets. It contains a state machine that monitors the status of GT and Interlaken (that is, GT lock and RX alignment) and sends traffic to the core. Similarly, the Interlaken_0_pkt_mon module is mainly responsible for reception and checking of packets from the core. It also contains a state machine that monitors the status of GT and INTERLAKEN (that is, GT lock and RX alignment) and receives traffic from the core.
Other optional modules instantiated in the example design are as follows:
- Interlaken_0_shared_logic_wrapper
- When you select Include GT subcore in example design or Include Shared Logic in example design in the ILKN/GT Selection and Configuration tab of the Interlaken IP Vivado IDE, this module will be available in the example design. This wrapper contains three modules: Interlaken_0_clocking_wrapper, Interlaken_0_reset_wrapper, and Interlaken_0_common_wrapper. The Interlaken_0_clocking_wrapper has the instantiation of the IBUFDS for the gt_ref_clk, and the Interlaken_0_reset_wrapper brings out the reset architecture instantiated between the core and the GT. The Interlaken_0_common_wrapper brings the transceiver common module out of the Interlaken IP core.
- Interlaken_0_gt_wrapper
- This module is present in the example design when you select the Include GT subcore in example design option from the ILKN/GT Selection and Configuration tab. This module instantiates the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the core.