Example Design Hierarchy - 2.4 English - PG169

The following figure shows the instantiation of various modules and their hierarchy in the example design.

Figure 1. Example Design Hierarchy

Details of the example design hierarchy are as follows:

• The interlaken_0 module instantiates Interlaken and the serial transceiver (GT) along with various helper blocks.
• The interlaken_0_pkt_gen_mon module instantiates the interlaken_0_gen_wrapper and interlaken_0_mon_wrapper modules.
• The interlaken_0_gen_wrapper module instantiates interlaken_0_pkt_gen (packet generator), in-band flow control generator (if IBFC is enabled in the AMD Vivado™ Design Suite (IDE)) and out-of-band flow control generator modules (if out-of-band flow control (OOBFC) is enabled in the Vivado IDE) based on ILKN Vivado IDE configuration.
• The interlaken_0_mon_wrapper module instantiates interlaken_0_pkt_mon (packet monitor), in-band flow control monitor (if IBFC is enabled in the Vivado IDE) and out-of-band flow control monitor (if OOBFC enabled in the Vivado IDE) modules based on ILKN Vivado IDE configuration.
• The interlaken_0_pkt_gen_mon and interlaken_0 modules handshake with each other using few signals: GT locked, RX alignment, and data transfer signals as per LBUS protocol. You can change the number of packets in the interlaken_0_exedes.v file using a parameter. The same number is used by the generator and monitor to send and receive packets. The number of packets should be even and in the range of 2 to 65534.
• The interlaken_0_pkt_gen module is mainly responsible for the generation of LBUS packets and generating control signals to flow control (IBFC and OOBFC) generator modules and error injection test. It contains a state machine which monitors the GT and Interlaken status (that is, GT lock and RX alignment) and sends traffic to Interlaken.
• Similarly, the interlaken_0_pkt_mon module is mainly responsible for reception of packets from Interlaken and monitoring status signals from flow control (IBFC and OOBFC) monitor modules and error injection status signals from Interlaken core. It also contain a state machine which monitors the GT and Interlaken status (that is, GT lock and RX alignment) and receives traffic from Interlaken.
• The example design supports both Packet mode and Burst mode. The LBUS packet length is predefined to make sure that all segments SOP and EOP are toggled.
  • For the Packet mode, channel number starts from 0 and increments for each packet up to 255 and resets back to 0.
  • For Burst mode, channel number toggles between two predefined channel numbers.
• The Swap Logic does bit swapping on the data interface between the Interlaken core and the GT.
• The transceiver_debug module is available in the example design when you enable the Additional transceiver control and status ports from the GT Selections and Configuration tab of the Interlaken Vivado IDE. This module brings out all the DRP ports of the transceiver module out of the Interlaken core.
• The GT_common module is available in the example design when you select the Include Shared Logic in example design from the GT Selections and Configuration tab of the Interlaken Vivado IDE. This module brings out the transceiver common module out of the Interlaken core.
• The clocking wizard generates different clocks based on the core configuration in the Interlaken Vivado IDE. If you set Line Rate to 12.5 Gb/s, the clocking wizard generates one clock with 300 MHz and the same clock is used as core_clk and lbus_clk. If you set Line Rate to 25.78125 Gb/s, the clocking wizard generates two clocks, lbus_clk with a frequency of 300 MHz and core_clk with a frequency of 412 MHz.
• The AXI4-Lite interface wrapper is available when you select the Include AXI4-Lite Control and Statistics Interface option from the General tab. This module is included inside the ilkn_0_wrapper. This wrapper contains two modules: ilkn_0_axi4_lite_reg_map and ilkn_0_axi4_lite_slave_2_ipif. These modules are described in detail in AXI4-Lite Interface Implementation.
• The AXI4-Lite user interface is available when you select the Include AXI4-Lite Control and Statistics Interface option from the General tab. This module is present in the ilkn_pkt_gen_mon. This module is described in detail in AXI4-Lite Interface Implementation.

Figure 2. 25 Gb/s Reference Clock