The dynamic reconfiguration port (DRP) allows the dynamic change of attributes in the
Integrated Interlaken IP core. The DRP interface is a processor-friendly
synchronous interface with an address bus (DRP_ADDR) and separated data
buses for reading (DRP_DO) and writing (DRP_DI)
configuration data to the ILKN block. An enable signal (DRP_EN), a
read/write signal (DRP_WE), and a ready/valid signal
(DRP_RDY) are the control signals that implement read and write
operations, indicate operation completion, or indicate the availability of data.
For the DRP to work, a clock must be provided to the DRP_CLK port. See
the following data sheets for the maximum allowed clock frequencies.
- Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
- Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
- Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
- Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
The ILKN block must be held in reset when you want to dynamically change the attributes
through the DRP. That is, TX_RESET, RX_RESET,
TX_SERDES_REFCLK_RESET, and the
RX_SERDES_RESET[11:0] signals need to be asserted High.