The DRP interface provides a means to change attribute values by over-writing memory
cells without re-configuring the entire FPGA or using partial reconfiguration. The
Interlaken core must be held in reset while the DRP port is used, and all external
timing requirements must be met. The memory cells is defined as multi-cycle paths in
core timing analysis, and the DRP requires several clock cycles before the new values
can be read (indicated by DRP_RDY assertion).The new set of attribute
values must contain a legal configuration of the Interlaken core before the core is
brought out of the reset state.
The DRP clock can be any continuously running clock not exceeding 250 MHz.