DRP Address Map of the ILKN Block in the UltraScale+ Device Architecture - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)
Document ID
PG169
Release Date
2024-06-05
Version
2.4 English

The following table lists the DRP map of the ILKN block in UltraScale+ devices sorted by address. All other addresses are reserved.

Table 1. DRP Address Map of the ILKN Block in UltraScale+ Devices
DRP Address (Hex) DRP Bits R/W Attribute Name Attribute Encoding (Hex) DRP Encoding (Hex)
6 [3:0] R/W CTL_TX_LAST_LANE[3:0] 0-B 0-B
C [3:0] R/W CTL_TX_FC_CALLEN[3:0] 0-F 0-F
12 0 R/W CTL_TX_DISABLE_SKIPWORD FALSE 0
TRUE 1
18 [15:0] R/W CTL_TX_MFRAMELEN_MINUS1[15:0] FF-1FFF FF-1FFF
1E [1:0] R/W CTL_TX_BURSTMAX[1:0] 0-3 0-3
24 [2:0] R/W CTL_TX_BURSTSHORT[2:0] 1-3 1-3
2A [3:0] R/W CTL_RX_LAST_LANE[3:0] 0-B 0-B
30 [15:0] R/W CTL_RX_MFRAMELEN_MINUS1[15:0] FF-1FFF FF-1FFF
36 [1:0] R/W CTL_RX_BURSTMAX[1:0] 0-3 0-3
3C 0 R/W MODE FALSE 0
TRUE 1
42 0 R/W BYPASS FALSE 0
TRUE 1
4E [13:0] R/W CTL_TX_RETRANS_DEPTH[13:0] 200-800 200-800
54 [2:0] R/W CTL_TX_RETRANS_MULT[2:0] 0-5 0-5
5A 0 R/W CTL_RX_PACKET_MODE FALSE 0
TRUE 1
60 [1:0] R/W CTL_RX_CHAN_EXT[1:0] 0-3 0-3
72 [2:0] R/W CTL_RX_RETRANS_MULT[2:0] 0-5 0-5
78 [15:0] R/W CTL_RX_RETRANS_TIMER1[15:0] 9-FFFF 9-FFFF
7E [15:0] R/W CTL_RX_RETRANS_TIMER2[15:0] 0-FFFF 0-FFFF
84 [3:0] R/W CTL_RX_RETRANS_RETRY[3:0] 2-F 2-F
8A [7:0] R/W CTL_RX_RETRANS_WRAP_TIMER[7:0] 0-FF 0-FF
90 [11:0] R/W CTL_RX_RETRANS_WDOG[11:0] 0-FFF 0-FFF
96 [1:0] R/W CTL_TX_CHAN_EXT[1:0] 0-3 0-3
9C [1:0] R/W CTL_TX_RETRANS_RAM_BANKS[1:0] 0-3 0-3