Core XCI Top-Level Port List - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)
Document ID
PG169
Release Date
2024-06-05
Version
2.4 English

The top-level port list for the core XCI is listed here.

Table 1. Core XCI Top-level Input and Output Ports
Name Size I/O Description
gt_ref_clk0_p 1 I Differential input clk to the GT.
gt_ref_clk0_n 1 I Differential input clk to the GT.
init_clk 1 I Stable input clk to the GT.
sys_reset 1 I Reset for interlaken_0.
gt_txusrclk2 1 O TX user clock output from the GT.
gt_rxusrclk2 1 O RX user clock output from the GT.
gt_tx_reset_done_inv 1 O TX user reset output from the GT.
gt_rx_reset_done_inv 1 O RX user reset output from the GT.
gt0_rxp_in 1 I Differential serial GT RX input for lane 0.
gt0_rxn_in 1 I Differential serial GT RX input for lane 0.
gt1_rxp_in 1 I Differential serial GT RX input for lane 1.
Note: This port is available when number of lanes is more than 1.
gt1_rxn_in 1 I Differential serial GT RX input for lane 1.
Note: This port is available when number of lanes is more than 1.
gt2_rxp_in 1 I Differential serial GT RX input for lane 2.
Note: This port is available when number of lanes is more than 2.
gt2_rxn_in 1 I Differential serial GT RX input for lane 2.
Note: This port is available when number of lanes is more than 2.
gt3_rxp_in 1 I Differential serial GT RX input for lane 3.
Note: This port is available when number of lanes is more than 3.
gt3_rxn_in 1 I Differential serial GT RX input for lane 3.
Note: This port is available when number of lanes is more than 3.
gt4_rxp_in 1 I Differential serial GT RX input for lane 4.
Note: This port is available when number of lanes is more than 4.
gt4_rxn_in 1 I Differential serial GT RX input for lane 4.
Note: This port is available when number of lanes is more than 4.
gt5_rxp_in 1 I Differential serial GT RX input for lane 5.
Note: This port is available when number of lanes is more than 5.
gt5_rxn_in 1 I Differential serial GT RX input for lane 5.
Note: This port is available when number of lanes is more than 5.
_rxp_in 1 I Differential serial GT RX input for lane 6.
Note: This port is available when number of lanes is more than 6.
gt6_rxn_in 1 I Differential serial GT RX input for lane 6.
Note: This port is available when number of lanes is more than 6.
gt7_rxp_in 1 I Differential serial GT RX input for lane 7.
Note: This port is available when number of lanes is more than 7.
gt7_rxn_in 1 I Differential serial GT RX input for lane 7.
Note: This port is available when number of lanes is more than 7.
gt8_rxp_in 1 I Differential serial GT RX input for lane 8.
Note: This port is available when number of lanes is more than 8.
gt8_rxn_in 1 I Differential serial GT RX input for lane 8.
Note: This port is available when number of lanes is more than 8.
gt9_rxp_in 1 I Differential serial GT RX input for lane 9.
Note: This port is available when number of lanes is more than 9.
gt9_rxn_in 1 I Differential serial GT RX input for lane 9.
Note: This port is available when number of lanes is more than 9.
gt10_rxp_in 1 I Differential serial GT RX input for lane 10.
Note: This port is available when number of lanes is more than 10.
gt10_rxn_in 1 I Differential serial GT RX input for lane 10.
Note: This port is available when number of lanes is more than 10.
gt11_rxp_in 1 I Differential serial GT RX input for lane 11.
Note: This port is available when number of lanes is more than 11.
gt11_rxn_in 1 I Differential serial GT RX input for lane 11.
Note: This port is available when number of lanes is more than 11.
gt0_txn_out 1 O Differential serial GT TX output for lane 0.
gt0_txp_out 1 O Differential serial GT TX output for lane 0.
gt1_txn_out 1 O Differential serial GT TX output for lane 1.
Note: This port is available when number of lanes is more than 1.
gt1_txp_out 1 O Differential serial GT TX output for lane 1.
Note: This port is available when number of lanes is more than 1.
gt2_txn_out 1 O Differential serial GT TX output for lane 2.
Note: This port is available when number of lanes is more than 2.
gt2_txp_out 1 O Differential serial GT TX output for lane 2.
Note: This port is available when number of lanes is more than 2.
gt3_txn_out 1 O Differential serial GT TX output for lane 3.
Note: This port is available when number of lanes is more than 3.
gt3_txp_out 1 O Differential serial GT TX output for lane 3.
Note: This port is available when number of lanes is more than 3.
gt4_txn_out 1 O Differential serial GT TX output for lane 4.
Note: This port is available when number of lanes is more than 4.
gt4_txp_out 1 O Differential serial GT TX output for lane 4.
Note: This port is available when number of lanes is more than 4.
gt5_txn_out 1 O Differential serial GT TX output for lane 5.
Note: This port is available when number of lanes is more than 5.
gt5_txp_out 1 O Differential serial GT TX output for lane 5.
Note: This port is available when number of lanes is more than 5.
gt6_txn_out 1 O Differential serial GT TX output for lane 6.
Note: This port is available when number of lanes is more than 6.
gt6_txp_out 1 O Differential serial GT TX output for lane 6.
Note: This port is available when number of lanes is more than 6.
gt7_txn_out 1 O Differential serial GT TX output for lane 7.
Note: This port is available when number of lanes is more than 7.
gt7_txp_out 1 O Differential serial GT TX output for lane 7.
Note: This port is available when number of lanes is more than 7.
gt8_txn_out 1 O Differential serial GT TX output for lane 8.
Note: This port is available when number of lanes is more than 8.
gt8_txp_out 1 O Differential serial GT TX output for lane 8.
Note: This port is available when number of lanes is more than 8.
gt9_txn_out 1 O Differential serial GT TX output for lane 9.
Note: This port is available when number of lanes is more than 9.
gt9_txp_out 1 O Differential serial GT TX output for lane 9.
Note: This port is available when number of lanes is more than 9.
gt10_txn_out 1 O Differential serial GT TX output for lane 10.
Note: This port is available when number of lanes is more than 10.
gt10_txp_out 1 O Differential serial GT TX output for lane 10.
Note: This port is available when number of lanes is more than 10.
gt11_txn_out 1 O Differential serial GT TX output for lane 11.
Note: This port is available when number of lanes is more than 11.
gt11_txp_out 1 O Differential serial GT TX output for lane 11.
Note: This port is available when number of lanes is more than 11.
tx_reset_done 1 I TX reset done input to the core from the reset wrapper logic.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
rx_reset_done 1 I RX reset done input to the core from the reset wrapper logic.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
axi_usr_tx_reset 1 O User TX reset from the AXI4-Lite register map module.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.
axi_usr_rx_reset 1 O User RX reset from the AXI4-Lite register map module.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.
axi_usr_rx_serdes_reset 12 O User RX SerDes reset from the AXI4-Lite register map module.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.
axi_usr_tx_serdes_refclk_reset 1 O RX SerDes clock out from the core to the reset wrapper.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
qpll0clk_in 12 I QPLL0 clock input.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
qpll0refclk_in 12 I QPLL0 ref clock input.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
qpll1clk_in 12 I QPLL1 clock input.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
qpll1refclk_in 12 I QPLL1 ref clock input.
Note: This port is available when the Include Shared Logic in option is selected as Example Design in the ILKN/GT Selection and Configuration tab.
gtwiz_reset_qpll0lock_in 3 I QPLL0 lock reset input to the GT.
Note: This port is available when the Include Shared Logic in option is selected as Example Design and PLL Type is selected as QPLL0 in the ILKN/GT Selection and Configuration tab.
gtwiz_reset_qpll0reset_out 3 O QPLL0 lock reset output from the GT.
Note: This port is available when the Include Shared Logic in option is selected as Example Design and PLL Type is selected as QPLL0 in the ILKN/GT Selection and Configuration tab.
gtwiz_reset_qpll1lock_in 3 I QPLL1 lock reset input to the GT.
Note: This port is available when the Include Shared Logic in option is selected as Example Design and PLL Type is selected as QPLL0 in the ILKN/GT Selection and Configuration tab.
gtwiz_reset_qpll1reset_out 3 O QPLL1 lock reset output from the GT.
Note: This port is available when the Include Shared Logic in option is selected as Example Design and PLL Type is selected as QPLL0 in the ILKN/GT Selection and Configuration tab.
rx_ovfout 1 O Receive LBUS overflow. If this signal is asserted, it means that the LBUS clock is too slow for the incoming data stream. The LBUS bandwidth must be greater than the Interlaken bandwidth.
rx_dataout0 128 O Receive segmented LBUS Data for segment0. The value of the bus is only valid in cycles in which RX_ENAOUT is sampled as 1.
rx_chanout0 11 O Receive channel number for segment0. The bus indicates the channel number of the in-flight packet and is only valid in cycles in which RX_ENAOUT is sampled as 1.

The maximum number of channels is programmed by the CTL_RX_CHAN_EXT pin. See that pin description for the encoding of that signal.
rx_enaout0 1 O Receive LBUS enable for segment0. This signal qualifies the other signals of the RX segmented LBUS Interface.

Signals of the RX LBUS Interface are only valid in cycles in which RX_ENAOUT is sampled as a 1.
rx_sopout0 1 O Receive LBUS Start of Packet for segment0. This signal indicates the SOP when it is sampled as a 1 and is only valid in cycles in which RX_ENAOUT is sampled as a 1.
rx_eopout0 1 O Receive LBUS EOP for segment0. This signal indicates the EOP when it is sampled as a 1 and is only valid in cycles in which RX_ENAOUT is sampled as a 1.
rx_errout0 1 O Receive LBUS error for segment0. This signal indicates that the current packet being received has an error when it is sampled as a 1. This signal is only valid in cycles when both rx_enaout and rx_eopout are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet being received.
rx_mtyout0 4 O Receive LBUS Empty for segment0. This bus indicates how many bytes of the RX_DATAOUT bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both RX_ENAOUT and RX_EOPOUT are sampled as 1. When RX_ERROUT and RX_ENAOUT are sampled as 1, the value of RX_MTYOUT[3:0] is always 000. Other bits of RX_MTYOUT are as usual.
rx_dataout1 128 O Receive segmented LBUS Data for segment1.
rx_chanout1 11 O Receive channel number for segment1.
rx_enaout1 1 O Receive LBUS enable for segment1.
rx_sopout1 1 O Receive LBUS Start of Packet for segment1.
rx_eopout1 1 O Receive LBUS EOP for segment1.
rx_errout1 1 O Receive LBUS Error for segment1.
rx_mtyout1 4 O Receive LBUS Empty for segment1.
rx_dataout2 128 O Receive segmented LBUS Data for segment2.
rx_chanout2 11 O Receive channel number for segment2.
rx_enaout2 1 O Receive LBUS enable for segment2.
rx_sopout2 1 O Receive LBUS Start of Packet for segment2.
rx_eopout2 1 O Receive LBUS EOP for segment2.
rx_errout2 1 O Receive LBUS Error for segment2.
rx_mtyout2 4 O Receive LBUS Empty for segment2.
rx_dataout3 128 O Receive segmented LBUS Data for segment3.
rx_chanout3 11 O Receive channel number for segment3.
rx_enaout3 1 O Receive LBUS enable for segment3.
rx_sopout3 1 O Receive LBUS Start of Packet for segment3.
rx_eopout3 1 O Receive LBUS EOP for segment3.
rx_errout3 1 O Receive LBUS Error for segment3.
rx_mtyout3 4 O Receive LBUS Empty for segment3.
tx_rdyout 1 O Transmit LBUS Ready. This signal indicates whether the Interlaken core TX path is ready to accept data and provides back-pressure to the user logic. A value of 1 means the user logic can pass data to the core. A value of 0 means the user logic must stop transferring data to the core. When TX_RDYOUT is asserted depends on a pre-determined value of FIFO fill.
tx_ovfout 1 O Transmit LBUS Overflow. This signal indicates whether you have violated the back pressure mechanism provided by the TX_RDYOUT signal. If TX_OVFOUT is sampled as a 1, a violation has occurred. You must design the rest of the user logic to prevent the overflow of the TX interface.
tx_datain0 128 I Transmit segmented LBUS Data for segment0. This bus receives input data from the user logic. The value of the bus is captured in every cycle that TX_ENAIN is sampled as 1.
tx_chanin0 11 I Transmit LBUS channel number for segment0. This bus receives the channel number for the packet being written. The value of the bus is captured in every cycle that TX_ENAIN is sampled as 1.The maximum number of channels is programmed by the

CTL_TX_CHAN_EXT pin. See that pin description for the encoding of that signal.
tx_enain0 1 I Transmit LBUS enable for segment0. This signal is used to enable the TX LBUS Interface. All signals on this interface

are sampled only in cycles in which TX_ENAIN is sampled as a 1.
tx_sopin0 1 I Transmit LBUS Start Of Packet for segment0. This signal is used to indicate the SOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN is sampled as a 1.
tx_eopin0 1 I Transmit LBUS EOP for segment0. This signal is used to indicate the EOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN is sampled as a 1.
tx_errin0 1 I Transmit LBUS Error for segment0. This signal is used to indicate a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN and TX_EOPIN are sampled as 1.
tx_mtyin0 4 I Transmit LBUS Empty for segment0. This bus is used to indicate how many bytes of the TX_DATAIN bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that TX_ENAIN and TX_EOPIN are sampled as 1. When TX_EOPIN and TX_ERRIN are sampled as 1, the value of TX_MTYIN[2:0] is ignored as treated as if it was 000. The other bits of TX_MTYIN are used as usual.
tx_bctlin0 1 I Transmit force insertion of Burst Control word for segment0. This input is used to force the insertion of a Burst Control Word. When TX_BCTLIN and TX_ENAIN, are sampled as 1, a Burst Control word is inserted before the data on the TX_DATAIN bus is transmitted even if one is not required to observe the BurstMax parameter.

This input is used by external schedulers that wish to reduce bandwidth lost due to observation of the BurstShort parameter. The use of an enhanced scheduling algorithm as described in the Interlaken Protocol Definition 1.2 is required.
tx_datain1 128 I Transmit segmented LBUS Data for segment1.
tx_chanin1 11 I Transmit LBUS channel number for segment1.
tx_enain1 1 I Transmit LBUS enable for segment1.
tx_sopin1 1 I Transmit LBUS Start Of Packet for segment1.
tx_eopin1 1 I Transmit LBUS EOP for segment1.
tx_errin1 1 I Transmit LBUS Error for segment1.
tx_mtyin1 4 I Transmit LBUS Empty for segment1.
tx_bctlin1 1 I Transmit force insertion of Burst Control word for segment1.
tx_datain2 128 I Transmit segmented LBUS Data for segment2
tx_chanin2 11 I Transmit LBUS channel number for segment2.
tx_enain2 1 I Transmit LBUS enable for segment2.
tx_sopin2 1 I Transmit LBUS enable for segment2.
tx_eopin2 1 I Transmit LBUS EOP for segment2.
tx_errin2 1 I Transmit LBUS Error for segment2.
tx_mtyin2 4 I Transmit LBUS Empty for segment2.
tx_bctlin2 1 I Transmit force insertion of Burst Control word for Segment2.
tx_datain3 128 I Transmit segmented LBUS Data for segment3.
tx_chanin3 11 I Transmit LBUS channel number for segment3.
tx_enain3 1 I Transmit LBUS enable for segment3.
tx_sopin3 1 I Transmit LBUS Start Of Packet for segment3.
tx_eopin3 1 I Transmit LBUS EOP for segment3.
tx_errin3 1 I Transmit LBUS Error for segment3.
core_tx_reset 1 I Asynchronous reset for the TX circuits. This signal is active-High (1= reset) and must be held High until all of the clocks for the TX path are fully active. These clocks are CORE_CLK, LBUS_CLK, and TX_SERDES_REFCLK.

The Interlaken core handles synchronizing the TX_RESET input to the appropriate clock domains within the core.
core_rx_reset 1 I Asynchronous reset for the RX circuits. This signal is active-High (1= reset) and must be held High until all of the clocks for the RX path are fully active. These clocks are CORE_CLK, LBUS_CLK, and RX_SERDES_CLK[11:0]. The Interlaken core handles synchronizing the RX_RESET input to the appropriate clock domains within the core.
tx_mtyin3 4 I Transmit LBUS Empty for segment3.
tx_bctlin3 1 I Transmit force insertion of Burst Control word for Segment3.
drp_clk 1 I DRP interface clock. When DRP is not used, this can be tied to GND.
core_drp_reset 1 I Core DRP reset.
gt_drp_done 1 I GT DRP done signal is asserted High for at least two clock cycles (drp_clk). This is to reset the GT after any GT DRP write operations are performed.
lockedn 1 I User output to drive tx_reset and rx_reset of Interlaken.
drp_en 1 I DRP enable signal.

0: No read or write operations performed.

1: Enables a read or write operation.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.
drp_we 1 I DRP write enable.

0: Read operation when DRP_EN is 1.

1: Write operation when DRP_EN is 1.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.
drp_addr 10 I DRP address bus.
drp_di 16 I Data bus for writing configuration data from the FPGA logic resources to the Interlaken core.
drp_do 16 O Data bus for reading configuration data from the ILKN to the FPGA logic resources.
usr_tx_reset 1 O TX reset output for the user.
usr_rx_reset 1 O RX reset output for the user.
drp_rdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
core_clk 1 I 300/412 MHz core clock. The minimum core clock frequency is 300 MHz for 12 x 12.5 Gb/s mode.
lbus_clk 1 I Rate-adapting FIFO clock for the user side logic. LBUS signals are synchronized to this clock.
gt_loopback_in 36 I GT loopback input signal.

See the UltraScale Architecture GTY Transceivers User Guide (UG578).
gt_eyescanreset 12 I For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_rxdfelpmreset 12 I For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_rxlpmen 12 I For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.

Port width: 10-bit for 100 Gigabit Attachment Unit Interface 10 (CAUI10) or Run time Selectable case and 4-bit width for CAUI4 mode)
gt_rxprbscntreset 12 I For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.

Port width: 10-bit for CAUI10 or Run time Selectable case and 4-bit width for CAUI4 mode)
gt_rxprbserr 12 O For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_rxprbssel 48 I Refer GT user guide for the port description.
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_rxresetdone 12 O For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_txprbssel 48 I For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_txresetdone 12 O For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_rxbufstatus 36 O For the port description, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
Note: This port is available when Enable Additional GT Control and Status Ports is selected from the GT Selection and Configuration tab.
gt_drpclk 1 I DRP interface clock.
gt0_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt0_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt0_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt0_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt0_drpaddr 10 I DRP address bus.
gt0_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt1_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt1_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt1_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt1_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt1_drpaddr 10 I DRP address bus.
gt1_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt2_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt2_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt2_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt2_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt2_drpaddr 10 I DRP address bus.
gt2_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt3_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt3_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt3_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt3_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt3_drpaddr 10 I DRP address bus.
gt3_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt4_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt4_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt4_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt4_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt4_drpaddr 10 I DRP address bus.
gt4_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt5_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt5_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt5_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt5_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt5_drpaddr 10 I DRP address bus.
gt5_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt6_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt6_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt6_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt6_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt6_drpaddr 10 I DRP address bus.
gt6_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt7_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt7_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt7_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt7_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt7_drpaddr 10 I DRP address bus.
gt7_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt8_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt8_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt8_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt8_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt8_drpaddr 10 I DRP address bus.
gt8_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt9_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt9_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt9_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt9_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt9_drpaddr 10 I DRP address bus.
gt9_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt10_drpdo 16 O Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt10_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt10_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt10_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.

gt10_drpaddr 10 I DRP address bus.
gt10_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt11_drpdo 16 I Data bus for reading configuration data from the GT transceiver to the FPGA logic resources.
gt11_drprdy 1 O Indicates operation is complete for write operations and data is valid for read operations.
gt11_drpen 1 I DRP enable signal.

0: No read or write operation performed.

1: Enables a read or write operation.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.
gt11_drpwe 1 I DRP write enable.

0: Read operation when DRPEN is 1.

1: Write operation when DRPEN is 1.

For write operations, DRPWE and DRPEN should be driven High for one DRPCLK cycle only.
gt11_drpaddr 10 I DRP address bus.
gt11_drpdi 16 I Data bus for writing configuration data from the FPGA logic resources to the transceiver.
gt_eyescantrigger 12 I Causes a trigger event.
gt_rxcdrhold 12 I Hold the clock data recovery (CDR) control loop frozen.
gt_rxpolarity 12 I The RXPOLARITY port can invert the polarity of incoming data:

0: Not inverted. RXP is positive and RXN is negative.

1: Inverted. RXP is negative and RXN is positive.
gt_rxrate 36 I Dynamic pins to automatically change effective PLL dividers in the GTH transceiver RX. These ports are used for PCI Express® and other standards.

000: Use RXOUT_DIV attributes

001: Divide by 1

010: Divide by 2

011: Divide by 4

100: Divide by 8

101: Divide by 16

110: Divide by 1

111: Divide by 1

RXBUF_RESET_ON_RATE_CHANGE attribute enables optional automatic reset.
gt_txdiffctrl 48 I Driver Swing Control. The default is user specified. All listed values are in mVPPD.
Note: The peak-to-peak differential voltage is defined when TXPOSTCURSOR = 5'b00000 and TXPRECURSOR = 5'b00000.
[3:0] mVPPD
4'b0000 269
4'b0001 336
4'b0010 407
4'b0011 474
4'b0100 543
4'b0101 609
4'b0110 677
4'b0111 741
4'b1000 807
4'b1001 866
4'b1010 924
4'b1011 973
4'b1100 1018
4'b1101 1056
4'b1110 1092
4'b1111 1119
gt_txpolarity 12 I The TXPOLARITY port is used to invert the polarity of outgoing data.

0: Not inverted. TXP is positive, and TXN is negative.

1: Inverted. TXP is negative, and TXN is positive.
gt_txpostcursor 60 I Transmitter post-cursor TX pre-emphasis control. The default is user specified. All listed values (dB) are typical.
Note: The TXPOSTCURSOR values are defined when the TXPRECURSOR =5'b00000.

Emphasis = 20log10(Vhigh/Vlow) = |20log10 (Vlow/Vhigh)|
gt_txprbsforceerr 12 I When this port is driven High, errors are forced in the pseudo-random binary sequence (PRBS) transmitter. While this port is asserted, the output data pattern contains errors. When TXPRBSSEL is set to 4'b0000, this port does not affect TXDATA.
gt_txprecursor 60 I Transmitter pre-cursor TX pre-emphasis control. The default is user specified. All listed values (dB) are typical.
Note: The TXPRECURSOR values are defined when the TXPOSTCURSOR =5'b00000.

Emphasis = 20log10(Vhigh/Vlow) = |20log10 (Vlow/Vhigh)|
gt_eyescandataerror 12 O Asserts high for one REC_CLK cycle when an (unmasked) error occurs while in the COUNT or ARMED state
gt_txbufstatus 24 O

TXBUFSTATUS provides status for the TX Buffer or the TX asynchronous gearbox. When using the TX asynchronous gearbox, the port status is as follows.

Bit 1:

  • 0: No TX asynchronous gearbox FIFO overflow.
  • 1: TX asynchronous gearbox FIFO overflow.

Bit 0:

  • 0: No TX asynchronous gearbox FIFO underflow.
  • 1: TX asynchronous gearbox FIFO underflow.

After the port is set High, it remains High until the TX asynchronous gearbox is reset.
gtpowergood_out 12 O Refer to the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for the port description.
gt_refclk_out 1 O gt_refclk_out which is the same as gt_ref_clk to drive user fabric logic.
ctl_tx_fc_stat 256 I TX In-Band Flow Control Input. These signals are used to set the status for each calendar position in the in-band-flow control mechanism (see the Interlaken Protocol Definition, Revision 1.2, October 7, 2008). A value of 1 means XON, a value of 0 means XOFF. These bits are transmitted in the Interlaken Control Word bits [55:40]. Each bit of CTL_TX_FC_STAT represents an entry in the flow control calendar with a length of 256 entries. When bit 56 of a Control Word is a value of 1, the first 16 calendar entries are output on bits 55-40. Specifically, Bit 55 of the first Control Word reflects the state of CTL_TX_FC_STAT[0], bit 54 reflects the state of CTL_TX_FC_STAT[1], bit 53 reflects the state of CTL_TX_FC_STAT[2], etc. as explained in the example in section 5.3.4.1 of Interlaken spec 1.1. Subsequent Control Words contain the next 16 calendar entries and so forth.

This input must be synchronous with LBUS_CLK.
stat_tx_underflow_err 1 O TX Underflow. This signal indicates if the LBUS interface is being clocked too slowly to properly fill the link with data. In normal operation, this signal is always sampled as 0. If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
stat_tx_burst_err 1 O TX BurstShort Error. When this signal is a value of 1, a burst (that is, a sequence of Data Words between two Control Words) was shorter than the value specified by CTL_TX_BURSTSHORT. This signal is only asserted if the final Control Word did not contain an EOP. This signal is provided to identify a poor scheduler design that results in reduced LBUS transaction errors. The TX core must be reset if this signal is asserted.
stat_tx_overflow_err 1 O TX Overflow. This output should never be asserted and indicates a critical failure. The core needs to be reset. This output is synchronous with the LBUS_CLK.
stat_rx_diagword_lanestat 12 O Lane Status messaging outputs. This bus reflects the most recent value in bit 33 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in STAT_RX_CRC32_VALID is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
stat_rx_diagword_intfstat 12 O Lane Status messaging outputs. This bus reflects the most recent value in bit 32 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in STAT_RX_CRC32_VALID is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
stat_rx_crc32_valid 12 O Diagnostic Word CRC32 Valid. This bus reflects the validity of the CRC32 in the most recently received Diagnostic Word for the respective lane. A value of 1 indicated the CRC32 was valid and a value of 0 indicated the CRC32 was invalid. See section 5.4.6 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
stat_rx_crc32_err 12 O Diagnostic Word CRC32 Error/Invalid. This bus provides indication of an invalid CRC32 in the Diagnostic Word for the respective lane. These signals are asserted with a value of 1 for one LBUS clock cycle each time an error is detected.
stat_rx_fc_stat 256 O

RX Flow control Outputs. These signals indicate the flow control status for all of the calendar positions of the received data. A value of 1 means XON, a value of 0 means XOFF.

These outputs reflect the information contained in bits 55-40 of the Control Words received by the RX. Only 256 In-Band flow control bits are supported. If a longer calendar is received, latter bits are ignored and are never output. If a shorter calendar is received, the bits of STAT_RX_FC_STAT that were not updated maintain their previous state. Each bit of STAT_RX_FC_STAT represents a received flow control calendar entry.

STAT_RX_FC_STAT[0] is the first received calendar entry, STAT_RX_FC_STAT[1] is the second received calendar entry, STAT_RX_FC_STAT[2] is the third received calendar entry, etc. as explained in the example in section 5.3.4.1 Interlaken Protocol Definition, Revision 1.2, October 7, 2008. Whenever a CRC24 or a loss of lane alignment occurs, all bits of STAT_RX_FC_STAT are set to a value of 0. This output is synchronous with the LBUS_CLK.
stat_rx_mubits 8 O RX Multiple-Use Control Bits. This bus contains the “Multi-Use” field of the Interlaken Control (see the Interlaken Protocol Definition, Revision 1.2, October 7, 2008). The value of the bus are Bits[31:24] of the most recently received Interlaken Control Word.
stat_rx_mubits_updated 1 O RX Multiple-Use/General Purpose Control Bits Updated.

This output indicates that STAT_RX_MUBITS has been updated and is asserted for one clock cycle.
stat_rx_word_sync 12 O 64B/67B Word Boundary Locked. These signals indicate whether a lane is 64B/67B word boundary locked. A 64B/67B word boundary lock occurs if a lane detects 64 consecutive valid framing patterns on Bits[65:64] as per the Interlaken Protocol Definition, Revision 1.2, October 7, 2008 Section 5.4.2. These signals are independent of both the Meta Frame Synchronization Word and Scrambler State Control Word. A value of 1 indicates the corresponding lane has achieved 64B/67B word boundary lock.
stat_rx_synced 12 O Word Boundary Synchronized. These signals indicate whether a lane is word boundary synchronized. A value of 1 indicates the corresponding lane has achieved word boundary synchronization as follows:
  1. 64B/67B Word Boundary Locked,
  2. Correctly receiving the Meta Frame Synchronization Word, and
  3. Correctly receiving the Scrambler State Control Word as described in sections 5.4.2, 5.4.3, and 5.4.4 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.

This output is synchronous with LBUS_CLK.
stat_rx_synced_err 12 O Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective lane. A value of 1 indicates the corresponding lane had a word boundary synchronization error.
stat_rx_framing_err 12 O Framing Error. These signals indicate that an illegal framing pattern was detected in the respective lane. A value of 1 indicates an error occurred.
stat_rx_bad_type_err 12 O Unexpected or Illegal Meta Frame Control Word Block Type. These signals indicate an unexpected or illegal Meta Frame Control Word Block Type was detected.

These signals can be used to collect the statistic "RX_Bad_Control_Error" as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008. A value of 1 indicates an error in the corresponding lane.
stat_rx_mf_err 12 O Meta Frame Synchronization Word Error. These signals indicate that an incorrectly formed Meta Frame Synchronization Word was detected in the respective lane. A value of 1 indicates an error occurred.
stat_rx_descram_err 12 O Scrambler State Control Word Error. These signals indicate a mismatch between the received Scrambler State Word and the expected value. A value of 1 indicates an error in the corresponding lane.
stat_rx_mf_len_err 12 O Meta Frame Length Error. These signals indicate whether a Meta Frame length mismatch occurred in the respective lane. A value of 1 indicates the corresponding lane is receiving Meta Frame of wrong length.
stat_rx_mf_repeat_err 12 O Meta Frame Consecutive Error. These signals indicate whether consecutive Meta Frame errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane.
stat_rx_aligned 1 O All Lanes Aligned/Deskewed. This signal indicates whether or not all lanes are aligned and deskewed. A value of 1 indicates all lanes are aligned and deskewed.

When this signal is a 1, the RX path is aligned and can receive packet data.
stat_rx_misaligned 1 O Alignment Error. This signal indicates that the lane aligner did not receive the expected Meta Frame Synchronization Word across all (active) lanes. This signal can be used to collect the statistic "RX_Alignment_Error" as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2, October 7, 2008.

This signal is not asserted until the Meta Frame Synchronization Word has been received at least once across all lanes. A value of 1 indicates the error occurred.
stat_rx_aligned_err 1 O Loss of Lane Alignment/Deskew. This signal indicates an error occurred during lane alignment or lane alignment was lost. A value of 1 indicates an error occurred.
stat_rx_crc24_err 1 O Control Word CRC24 Error. This signal indicates whether or not a mismatch occurred between the received and the expected CRC24 value. A value of 1 indicates a mismatch occurred.
stat_rx_msop_err 1 O Missing Start of Packet Error. This signal indicates that a Missing Start of Packet was detected (and corrected).
stat_rx_meop_err 1 O Missing EOP Error. This signal indicates that a Missing EOP was detected (and corrected).
stat_rx_overflow_err 1 O RX FIFO Overflow Error. This signal indicates if the LBUS interface is being clocked too slowly to properly receive the data being transmitted across the link. A value of 1 indicates an error occurred.

In normal operation, this signal is always sampled as 0.

If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
stat_rx_burstmax_err 1 O Interlaken RX BurstMax. This bus set the BurstMax parameter for the RX as follows:

0x0 = 64 bytes

0x1 = 128 bytes

0x2 = 192 bytes

0x3 = 256 bytes

These inputs are only used with STAT_RX_BURSTMAX_ERR.
stat_rx_burst_err 1 O Burst Error. This signal indicates that a BurstShort or a burst length error was detected.
txdata_in 768 O Core TX user data in when GT is present in the example design.
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
rxdata_out 768 I Core RX user data in when GT is present in example design.
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
tx_clk 1 I TX user clock
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
rx_clk 1 I RX user clock
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
axi_gt_reset_all 1 O User reset from the AXI4-Lite register map module.
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
axi_gt_loopback 1 O GT loopback signal to GT driven through AXI.
Note: This port is available for configurations when Include GT subcore in example design is selected from the ILKN/ GT Selection and Configuration tab.
Note: AXI4-Lite interface ports are visible only when you select Include AXI4-Lite Control and Statistics Interface option from General tab. For the AXI4-Lite interface port list and description, see AXI4-Lite User Interface Ports.