This guide describes the function and operation of the AMD integrated IP core for Interlaken, including how to design, customize, and implement it. The Integrated Interlaken IP core is a high-performance, low-power, flexible implementation of the Interlaken protocol, based on the Interlaken Protocol definition Revision 1.2. The Integrated Interlaken IP core is a highly configurable integrated IP core that can support an overall bandwidth up to 150 Gb/s for protocol logic transmission.
The core instantiates the Integrated Interlaken IP core found in AMD UltraScale+™ and AMD UltraScale™ devices. This core simplifies the design process and reduces time to market.
Using the latest serial transceiver technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. In addition, Interlaken uses two levels of cyclic redundancy check (CRC) and a synchronous data scrambler to ensure data integrity and link robustness. For details on the core, see Product Specification.