Required Constraints
The Integrated Interlaken IP core solution requires the specification of timing and other physical implementation constraints to meet the specified performance requirements. These constraints are provided in a Xilinx Device Constraints (XDC) file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design of the Integrated Interlaken IP core.
To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD design tools. For additional details on the definition and use of an XDC specific constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903).
Constraints provided in the Integrated Interlaken IP core have been verified through implementation and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.