Data to be transmitted is written into the TX LBUS interface. When the
CTL_TX_RETRANS_ENABLE is enabled, the TX retransmission logic
writes the TX data into the retransmission buffer using the signals
STAT_TX_RETRANS_RAM_WDATA,
STAT_TX_RETRANS_RAM_WE_Bx, and
STAT_TX_RETRANS_RAM_WADDR. Data is read from the buffer using the
signals CTL_TX_RETRANS_RAM_RDATA,
STAT_TX_RETRANS_RAM_RD_Bx, and
STAT_TX_RETRANS_RAM_RADDR.
The buffer can contain up to four banks. Each bank consists of 11 parallel instances of
64 x 512 RAMB36 SDP block RAM to create a memory that is 644 bits wide and 512 entries
deep. Each RAM is configured with DO_REG = 1. The number of banks
required depends upon latency and is selected using the inputs
CTL_TX_RETRANS_RAM_BANKS[1:0].
All banks share a common write bus and write address. Each bank has its own write enable
signal: STAT_TX_RETRANS_RAM_WE_Bx.
All banks share a common read address. Each bank has its own read enable signal:
STAT_TX_RETRANS_RAM_RD_Bx. The read output of each bank goes into a
4:1 multiplexer. Bank 0 is selected when the multiplexer select signals are a value of
0. Bank 1 is selected when the multiplexer select signals are a value of 1 and so forth.
The signals STAT_TX_RETRANS_RAM_RSEL are used to control the
multiplexer.
The output of the multiplexer goes to a flip-flop pipeline stage which need not be reset.
The output of pipeline stage goes to CTL_TX_RETRANS_RAM_RDATA.
See the following figure.
In UltraScale+ devices, the TX retransmission logic is enhanced to allow up to two stages of pipeline in the fabric for all signals on the write path to the RAM banks.