Clocking - 2.4 English - PG169

The Integrated Interlaken IP core has the following major clock domains:

LBUS_CLK

The LBUS_CLK drives logic for both the RX and TX LBUS interfaces and the rate adapter. The LBUS_CLK is also the clock for most of the control and status signals. Exceptions are noted in the port descriptions. See the section on port description for more information.

CORE_CLK

The CORE_CLK is used to clock the protocol logic portion of the design.

RX Serial Transceiver Domain

Each serial transceiver lane has its own recovered clock. The RX_SERDES_CLK[11:0] is used for all of the logic for all serial transceiver receive lanes and the receive portion of Interlaken lane logic.

When the GT RX buffer is enabled, all the RX_SERDES_CLK[11:0] clocks share a single common clock.

TX Serial Transceiver Domain

The TX_SERDES_REFCLK is used for all of the logic for all serial transceiver transmit lanes and the transmit portion of Interlaken lane logic.

DRP_CLK

This clock is optional and necessary only for DRP operations. A comfortable frequency up to 250 MHz can be used.

The following table shows the typical clock frequencies for each Interlaken configuration. See the following data sheets for minimum and maximum allowable clock frequencies across speed grades.

• Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
• Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
• Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
• Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)