Port Changes
Added the gtpowergood_out and gt_refclk_out ports to Core XCI Top-Level Port List.
Attribute Changes
- Updated Attribute Encoding and DRP Encoding for CTL_TX_LAST_LANE[3:0] and CTL_RX_LAST_LANE[3:0] in DRP Address Map of the ILKN Block in the UltraScale Device Architecture and DRP Address Map of the ILKN Block in the UltraScale+ Device Architecture.
- Updated DRP Address, Attribute Encoding and DRP Encoding for CTL_TX_LAST_LANE[3:0] and CTL_RX_LAST_LANE[3:0] in DRP Address Map of the ILKN Block in the UltraScale Device Architecture and DRP Address Map of the ILKN Block in the UltraScale+ Device Architecture.