CTL_TX_RLIM_INTV[7:0] - 2.4 English - PG169

Integrated Interlaken 150G LogiCORE IP Product Guide (PG169)

Document ID
PG169
Release Date
2024-06-05
Version
2.4 English

This input specifies the update interval: the number of Local bus clock cycle between additions to the token bucket. The value of this input should not be changed when CTL_TX_RLIM_ENABLE is a value of 1.

Note: AMD recommends values between 8 and 32 for this input.