The interface ports are listed and described in the following table.
| Name | Size | I/O | Description |
|---|---|---|---|
| S_AXI_ACLK | 1 | I | AXI clock signal. |
| S_AXI_SRESET | 1 | I | AXI active-High synchronous reset. |
| S_AXI_PM_TICK | 1 | I | PM tick user input. |
| S_AXI_AWADDR | 32 | I | AXI write address. |
| S_AXI_AWVALID | 1 | I | AXI write address valid. |
| S_AXI_AWREADY | 1 | O | AXI write address ready. |
| S_AXI_WDATA | 32 | I | AXI write data. |
| S_AXI_WSTRB | 4 | I | AXI write strobe. This signal indicates which byte lanes hold valid data. |
| S_AXI_WVALID | 1 | I | AXI write data valid. This signal indicates that valid write data and strobes are available. |
| S_AXI_WREADY | 1 | O | AXI write data ready. |
| S_AXI_BRESP | 2 | O | AXI write response. This signal indicates the status of the write
transaction. ‘b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
| S_AXI_BVALID | 1 | O | AXI write response valid. This signal indicates that the channel is signaling a valid write response. |
| S_AXI_BREADY | 1 | I | AXI write response ready. |
| S_AXI_ARADDR | 32 | I | AXI read address. |
| S_AXI_ARVALID | 1 | I | AXI read address valid. |
| S_AXI_ARREADY | 1 | O | AXI read address ready. |
| S_AXI_RDATA | 32 | O | AXI read data issued by slave. |
| S_AXI_RRESP | 2 | O | AXI read response. This signal indicates the status of the read
transfer. ‘b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
| S_AXI_RVALID | 1 | O | AXI read data valid. |
| S_AXI_RREADY | 1 | I | AXI read ready. This signal indicates the user/master can accept the read data and response information. |