If you want to instantiate AXI4-Lite interface
to access the control and status registers of the ILKN core, check the Include AXI4-Lite Control and Statistics Interface check
box in the General tab. It
enables ilkn_0_axi4_lite_if_wrapper module (that
contains ilkn_0_axi4_lite_reg_map along with the ilkn_0_axi4_lite_slave_2_ipif module) in the ilkn_0_wrapper. The user interface logic (ilkn_0_axi4_lite_user_if) used for accessing the registers
(control, status, and statistics) is present in ilkn_0_pkt_gen_mon module.
This mode enables the following features:
- Configure all the CTL ports of the core through AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface. The address location with the configuration register list is found in Configuration Register Space.
- Access all the status and statistics registers from the core through AXI4-Lite interface. This is performed by reading the address locations for the status and statistics registers through register map. Status and Statistics Register Space shows the address with the corresponding register descriptions.
The following diagram shows the implementation when the Include AXI4-Lite Control and Statistics Interface option is selected.