ip\<component name>\example_design\ - ip\<component name>\example_design\ - 3.6 English

ip\<component name>\example_design\ - ip\<component name>\example_design\ - 3.6 English - PG168

7 Series FPGAs Transceivers Wizard (PG168)

Document ID

PG168

Release Date

2022-05-19

Version

3.6 English

Verilog/VHDL files for example design.

Table 5-11: ip\<component name>\example_design\
Name	Description
tx_startup_fsm.v[hd]	Reset module for transmitter. This file is not generated for GTZ transceivers.
rx_startup_fsm.v[hd]	Reset module for receiver. This file is not generated for GTZ transceivers.