Port Descriptions - Port Descriptions - 3.6 English

Table: Port List describes the input and output ports provided by the 7 series FPGAs transceivers circuit. Some ports are optional, and those are optionally selected based upon the protocol selection. The availability of the ports is controlled by user-selected parameters. For example, the Aurora 64B/66B protocol template does not have a TXINHIBIT port, but the CPRI protocol template includes a TXINHIBIT optional port when generating through the Wizard. Any port that is not exposed is appropriately tied off.

Table 2-1: Port List
Port	Direction	Clock Domain	Description
GTREFCLK_PAD_N_IN/ GTREFCLK_PAD_P_IN	Input	-	External differential clock input pin pair for the reference clock of the 7 series FPGA transceiver Quad.
SYSCLK_IN	Input	-	System clock is used to drive the FPGA logic in the example design. When the DRP interface is enabled, DRP_CLK_IN is connected to SYSCLK_IN in the example design. This clock needs to be constrained in the Xilinx Design Constraints (XDC).
DRP_CLK_IN_P/ DRP_CLK_IN_N	Input	-	External differential clock input pin pair for the DRP interface clock. This clock needs to be constrained in the XDC. See the 7 series data sheets for more information.
TRACK_DATA_OUT	Output	rxusrclk	Indicates that valid data is received on the RX side. It is a level signal synchronous to RXUSRCLK2.
RXN_IN/RXP_IN	Input	RX serial clk	RXP and RXN are the differential input pairs for each of the receivers in the 7 series FPGA transceiver Quad.
TXN_OUT/TXP_OUT	Output	TX serial clk	TXP and TXN are the differential output pairs for each of the transmitters in the 7 series FPGA transceiver Quad.

Table: Optional Ports for GTZ Transceivers describes the optional ports for GTZ transceivers.

Table 2-2: Optional Ports for GTZ Transceivers
Options	Direction	Clock Domain	Description
TXFIBRESET	Input	Async	Brings out the TXFIBRESET ports to the example design from which you can control the RESET of the FIB portion of the GTZ transceiver.
RXFIBRESET	Input	Asyc	Brings out the RXFIBRESET ports to the example design from which you can control the RESET of the FIB portion of the GTZ transceiver.
TXFIFOSTATUS	Output	txusrclk[0..7] based on TXUSRCLK_SEL _LANEn setting	This brings out the TXFIFOSTATUS port to the example design allowing you to learn the FIFO status.
RXFIFOSTATUS	Output	rxusrclk[0..7] based on RXUSRCLK_SEL _LANEn setting	This brings out the RXFIFOSTATUS port to the example design allowing you to learn the FIFO status.
TXRATESEL	Input	Async	Brings the TXRATESEL ports out onto the example top level. These ports are used to control the TX PLL divider ratios.
RXRATESEL	Input	Async	Brings the RXRATESEL ports out onto the example top level. These ports are used to control the RX PLL divider ratios.
TXPOLARITY	Input	Async	Brings out the TXPOLARITY port to the example design.
RXPOLARITY	Input	Async	Brings out the RXPOLARITY port to the example design.
TXEN	Input	Async	Brings out the TXEN port to the example design.
RXEN	Input	Async	Brings out the RXEN port to the example design.
TXOUTPUTEN	Input	Async	Brings out the TXOUTPUTEN port to the example design.
TXATTNCTRL	Input	Async	Brings out the TXATTNCTRL port to the example design.
TXEQPOSTCTRL	Input	Async	Brings out the TXEQPOSTCTRL port to the example design.
TXEQPRECTRL	Input	Async	Brings out the TXEQPRECTRL port to the example design.
TXSLEWCTRL	Input	txusrclk0..7] based on TXUSRCLK_SEL _LANEn setting	Brings out the TXSLEWCTRL port to the example design.
RXBITSLIP	Input	rxusrclk[0..7] based on RXUSRCLK_SEL _LANEn setting	Brings out the RXBITSLIP port onto the example design. This port can be used to slip data in raw mode.
RXSIGNALOK	Output	rxusrclk[0..7] based on RXUSRCLK_SEL _LANEn setting	Brings out the RXSIGNALOK port onto the example design.
CORECNTL	Input	Async	Brings out the CORECNTL ports onto the example design.
REFSEL	Input	Async	Brings out the REFSEL ports onto the example design.
PLLRECALEN	Input	Async	Brings out the PLLRECALEN ports onto the example design.
RXPRBS	Input	Async	Brings out all the RXPRBS related ports onto the example design.
TXPRBS	Input	Async	Brings out all the TXPRBS related ports onto the example design.
LOOPBACK	Input	Async	Brings out all the LOOPBACK control ports onto the example design.

Table: 8B/10B Optional Ports describes the 8B/10B optional ports.

Table 2-3: 8B/10B Optional Ports
Option		Direction	Clock Domain	Description
TX	TXBYPASS8B10B	Input	txusrclk	2-bit wide port disables 8B/10B encoder on a per-byte basis. High-order bit affects high-order byte of datapath.
	TXCHARDISPMODE	Input	txusrclk	2-bit wide ports control disparity of outgoing 8B/10B data. High-order bit affects high-order byte of datapath.
	TXCHARDISPVAL	Input	txusrclk
RX	RXCHARISCOMMA	Output	txusrclk	2-bit wide port flags valid 8B/10B comma characters as they are encountered. High-order bit corresponds to high-order byte of datapath.
RX	RXCHARISK	Output	txusrclk	2-bit wide port flags valid 8B/10B K characters as they are encountered. High-order bit corresponds to high-order byte of datapath.
Note: Options not used by the XAUI example are shaded.

Table: Optional Ports shows the optional ports available for latency and clocking.

Table 2-4: Optional Ports
Option	Direction	Clock Domain	Description
TXPCSRESET	Input	Async	Active-High reset signal for the transmitter physical coding sublayer (PCS) logic.
TXBUFSTATUS	Output	txusrclk2	2-bit signal monitors the status of the TX elastic buffer. This option is not available when the TX buffer is bypassed.
TXRATE	Input	txusrclk2	Transmit rate change port.
RXPCSRESET	Input	Async	Active-High reset signal for the receiver PCS logic.
RXBUFSTATUS	Output	rxusrclk2	Indicates condition of the RX elastic buffer. Option is not available when the RX buffer is bypassed.
RXBUFRESET	Input	Async	Active-High reset signal for the RX elastic buffer logic. This option is not available when the RX buffer is bypassed.
RXRATE	Input	rxusrclk2	Receive rate change port.
QPLLPD	Input	Async	Visible only when GTX or GTH transceiver is selected. Powerdown port for QPLL.
CPLLPD	Input	Async	Visible only when GTX or GTH transceiver is selected. Powerdown port for channel PLL (CPLL).
PLL0PD	Input	Async	Visible only when GTP transceiver is selected. Powerdown port for PLL0.
PLL1PD	Input	Async	Visible only when GTP transceiver is selected. Powerdown port for PLL1.
Note: Options not used by the XAUI example are shaded.

Table: Transceiver Control and Status Interface shows transceiver core debug ports that enable debug and control of the core for users wanting to drop the 7 series FPGAs Transceivers Wizard core into their designs.

Table 2-5: Transceiver Control and Status Interface
Port Names	XAUI	RXAUI	QSGMII	GigE PCS/PMA⁽¹⁾	DisplayPort	SRIO Gen2	Aurora 8B10B	Aurora 64B66B	JESD204	OBSAI	CPRI	10GBASE-R	10GBASE-KR
TXCHARDISPMODE	No	No	Yes	Yes	Yes	No	Yes	No	No	N/A	No	No	No
TXCHARDISPVAL	No	No	Yes	Yes	Yes	No	Yes	No	No	N/A	No	No	No
RXCHARISCOMMA	Yes	Yes	Yes	Yes	No	Yes	Yes	No	Yes	N/A	Yes	No	No
RXCHARISK	Yes	Yes	Yes	Yes	Yes	Yes	Yes	No	Yes	N/A	Yes	No	No
RXSTARTOFSEQ	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXPCSRESET	No	No	No	No	Yes	Yes	No	No	No	N/A	No	No	No
TXPMARESET	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXBUFSTATUS	No	No	Yes	Yes	Yes	Yes	Yes	No	No	N/A	No	Yes	Yes
RXPCSRESET	No	No	No	No	Yes	Yes	No	No	No	N/A	No	No	No
RXPMARESET	No	No	No	No	Yes	No	No	No	No	N/A	No	No	No
RXBUFSTATUS	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	No	No
RXBUFRESET	Yes	Yes	Yes	Yes	Yes	Yes	No	No	Yes	N/A	Yes	No	No
RXSLIDE	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXBYTEISALIGN	Yes	Yes	Yes	Yes	Yes	Yes	Yes	No	Yes	N/A	Yes	No	No
RXBYTEREALIGN	Yes	Yes	Yes	Yes	No	Yes	Yes	No	Yes	N/A	Yes	No	No
RXCOMMADET	Yes	Yes	Yes	Yes	No	Yes	Yes	No	Yes	N/A	Yes	No	No
TXPOLARITY	Yes	Yes	Yes	Yes	No	No	Yes	Yes	Yes	N/A	Yes	Yes	Yes
TXINHIBIT	No	No	No	No	Yes	Yes	No	No	No	N/A	No	No	No
TXDIFFCTRL	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	Yes	No
TXPOSTCURSOR	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	Yes	No
TXPRECURSOR	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	Yes	No
TXMAINCURSOR	No	No	No	No	No	No	Yes	Yes	No	N/A	No	No	No
TXQPISENN	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXQPISENP	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXQPIBIASEN	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXQPIWEAKPUP	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXQPISTRONGPDOWN	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXPOLARITY	Yes	Yes	Yes	Yes	No	No	Yes	Yes	Yes	N/A	Yes	Yes	Yes
RXDFELPMRESET	Yes	Yes	Yes	Yes	Yes	No	No	Yes	Yes	N/A	Yes	No	No
RXDFEAGCOVRDEN	No	No	Yes	Yes	No	No	No	Yes	No	N/A	No	No	No
RXLPMLFKLOVRDEN	No	No	No	No	No	No	No	Yes	No	N/A	No	No	No
RXLPMHFOVRDEN	No	No	No	No	No	No	No	Yes	No	N/A	No	No	No
RXLPMHFHOLD (GTP)	Yes	Yes	Yes	Yes	Yes	No	Yes	No	Yes	N/A	Yes	No	No
RXLPMLFHOLD (GTP)	Yes	Yes	Yes	Yes	Yes	No	Yes	No	Yes	N/A	Yes	No	No
RXQPIEN	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXQPISENN	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXQPISENP	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXLPMEN	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
TXPRBSSEL	Yes	Yes	Yes	Yes	Yes	No	No	No	Yes	N/A	Yes	No	No
TXPRBSFORCEERR	Yes	Yes	Yes	Yes	Yes	No	No	No	Yes	N/A	Yes	Yes	Yes
RXPRBS_LOOPBACK			Yes	Yes	No	No	No	No	No	N/A	No	No	No
RXPRBSCNTRESET	Yes	Yes	Yes	Yes	Yes	Yes	No	No	Yes	N/A	Yes	No	No
RXPRBSERR	Yes	Yes	Yes	Yes	Yes	Yes	No	No	Yes	N/A	Yes	No	No
RXPRBSSEL	Yes	Yes	Yes	Yes	Yes	Yes	No	No	Yes	N/A	Yes	No	No
LOOPBACK	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	Yes	N/A	Yes	No	No
COMWAKEDET	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXDETECTRX	No	No	No	No	No	No	No	No	No	N/A	No	No	No
RXSTATUS	No	No	No	No	No	No	No	No	Yes	N/A	Yes	No	No
TXCOMMIT	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXELECIDLE	Yes	Yes	Yes	Yes	No	Yes	No	No	No	N/A	No	No	No
RXVALID	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXCOMSAS	No	No	No	No	No	No	No	No	No	N/A	No	No	No
PHYSTATUS	No	No	No	No	No	No	No	No	No	N/A	No	No	No
COMINITDET	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXCOMWAKE	No	No	No	No	No	No	No	No	No	N/A	No	No	No
COMSASDET	No	No	No	No	No	No	No	No	No	N/A	No	No	No
COMFINISH	No	No	No	No	No	No	No	No	No	N/A	No	No	No
TXPD	Yes	Yes	Yes	Yes	Yes	No	Yes	No	Yes	N/A	Yes	No	No
RXPD	Yes	Yes	Yes	Yes	Yes	No	Yes	No	Yes	N/A	Yes	No	No
TXRESETDONE	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	No	No
RXRESETDONE	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	No	No
DRPADDR	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
DRPEN	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
DRPDI	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
DRPWE	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
DRPRDY	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
DRPDO	Yes	Yes	Yes	Yes	Yes	No	Yes	Yes	Yes	N/A	Yes	No	No
RXDISPERR	Yes	Yes	Yes	Yes	Yes	Yes	Yes	No	Yes	N/A	Yes	No	No
RXNOTINTABLE	Yes	Yes	Yes	Yes	Yes	Yes	Yes	No	Yes	N/A	Yes	No	No
EYESCANDATAERROR	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	N/A	Yes	Yes	Yes
EYESCANRESET	Yes	Yes	Yes	Yes	No	No	No	No	Yes	N/A	Yes	Yes	Yes
EYESCANTRIGGER	Yes	Yes	Yes	Yes	No	No	No	No	Yes	N/A	Yes	Yes	Yes
RXMONITOROUT	Yes	Yes	Yes	Yes	No	No	No	No	Yes	N/A	Yes	No	No
RXMONITORSEL	Yes	Yes	Yes	Yes	No	No	No	No	Yes	N/A	Yes	No	No
RXRATE	Yes	Yes	Yes	No	No	No	No	No	No			Yes	Yes
RXCDRHOLD	No	No	No	No	No	No	No	No				Yes	Yes
Notes: 1.Changes applicable to both protocol templates: gigabit_ethernet_CC and gigabit_ethernet_noCC.

Table: GTX and GTH Transceiver Debug Ports shows transceiver debug ports that are available in all protocol templates for GTX and GTH transceivers.

Table 2-6: GTX and GTH Transceiver Debug Ports
Name	Direction	Clock Domain	Width	Description
DRP
drpclk_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPCLK on transceiver channel
drpaddr_in	Input	drp_clk_in	drp_addr_width x Num. channels	Connects to DRPADDR on transceiver channel primitives. See 7-series Architecture GTX/ GTH Transceivers User Guide(UG476) for more information on drp_addr_width.
drpdi_in	Input	drp_clk_in	16 × Num. channels	Connects to DRPDI on transceiver channel primitives
drpen_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPEN on transceiver channel primitives
drpwe_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPWE on transceiver channel primitives
drpdo_out	Output	drp_clk_in	1 × Num. channels	Connects to DRPDO on transceiver channel primitives
drprdy_out	Output	drp_clk_in	1 × Num. channels	Connects to DRPRDY on transceiver channel primitives
TX reset and Initialization
gt_gttxreset_in	Input	sysclk_in	1 × Num. channels	Connects to GTTXRESET on transceiver channel primitives
gt_txpmareset_in	Input	Async	1 × Num. channels	Resets the TX PMA. Driven High, then deasserted to start the TX PMA reset process. Activating this port resets both the TX PMA and the TX PCS.
gt_txpcsreset_in	Input	Async	1 × Num. channels	Resets the TX PCS. Driven High, then deasserted to start the PCS reset process. Activating this port only resets the TX PCS.
gt_txuserrdy_in	Input	Async	1 × Num. channels	Connects to TXUSERRDY on transceiver channel primitives
gt_txresetdone_ out	Output	txusrclk2	1 × Num. channels	Indicates the GTX/GTH transceiver TX has finished reset and is ready for use. Driven Low when gttxreset goes High and not driven High until the GTX/GTH transceiver TX detects txuserrdy High.
RX reset and Initialization
gt_gtrxreset_in	Input	sysclk_in	1 × Num. channels	Connects to GTRXRESET on transceiver channel primitives
gt_rxpmareset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX PMA reset process.
gt_rxpcsreset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX PMA reset process. The rxpcsreset signal does not start the reset process until rxuserrdy is High.
gt_rxbufreset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX elastic buffer reset process. In either single or sequential mode, activating rxbufreset resets the RX elastic buffer only.
gt_rxuserrdy_in	Input	Async	1 × Num. channels	Connects to RXUSERRDY on transceiver channel primitives
gt_rxpmaresetdone_out	Output	Async	1 × Num. channels	Indicates that the RX PMA reset is complete. Driven Low when GTRXRESET or RXPMARESET is asserted. Available for duplex and RX-only simplex configurations. Available only with GTH transceivers.
gt_rxresetdone_out	Output	rxusrclk2	1 × Num. channels	When asserted, indicates the GTX/GTH transceiver RX has finished reset and is ready for use. Driven Low when gtrxreset is driven High. Not driven High until rxuserrdy goes High.
gt_txbufstatus_out	Output	txusrclk2	2 × Num. channels	txbufstatus[1]: TX buffer overflow or underflow status. Whentxbufstatus[1] is set High, the signal remains High until the TX buffer is reset. 1: TX FIFO has overflow or underflow. 0: No TX FIFO overflow or underflow error. txbufstatus[0]: TX buffer fullness. 1: TX FIFO is at least half full. 0: TX FIFO is less than half full.
gt_rxbufstatus_o ut	Output	rxusrclk2	3 × Num. channels	RX buffer status. 000b: Nominal condition. 001b: Number of bytes in the buffer are less than CLK_COR_MIN_LAT. 010b: Number of bytes in the buffer are greater than CLK_COR_MAX_LAT. 101b: RX elastic buffer underflow. 110b: RX elastic buffer overflow.
gt_txphaligndon e_out	Output	Async	1 × Num. channels	Connects to TXPHALIGNDONE on transceiver channel primitives
gt_txphinitdone_ out	Output	Async	1 × Num. channels	Connects to TXPHINITDONE on transceiver channel primitives
gt_txdlysresetdo ne_out	Output	Async	1 × Num. channels	Connects to TXDLYSRESETDONE on transceiver channel primitives
gt_rxphaligndon e_out	Output	Async	1 × Num. channels	Connects to RXPHALIGNDONE of transceiver channel primitives
gt_rxdlysresetdo ne_out	Output	Async	1 × Num. channels	Connects to RXDLYSRESETDONE of transceiver channel primitives
gt_rxsyncdone_o ut	Output	Async	1 × Num. channels	Connects to RXSYNCDONE of transceiver channel primitives
cplllock_out	Output	Async	1 × Num. channels	Active-High PLL frequency lock signal indicating that PLL frequency is within the predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met.
qplllock_out	Output	Async	1 × Num. channels	Active-High PLL frequency lock signal. Indicates that the PLL frequency is within predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met.
Signal Integrity and Functionality
gt_eyescantrigge r_in	Input	rxusrclk2	1 × Num. channels	Connects to EYESCANTRIGGER on transceiver channel primitives
gt_eyescanreset_ in	Input	Async	1 × Num. channels	Connects to EYESCANRESET on transceiver channel primitives
gt_eyescandatae rror_out	Output	Async	1 × Num. channels	Connects to EYESCANDATAERROR on transceiver channel primitives
gt_loopback_in	Input	Async	3 × Num. channels	Connects to LOOPBACK on transceiver channel primitives
gt_rxpolarity_in	Input	rxusrclk2	1 × Num. channels	Connects to RXPOLARITY on transceiver channel primitives
gt_txpolarity_in	Input	txusrclk2	1 × Num. channels	Connects to TXPOLARITY on transceiver channel primitives
gt_rxdfelpmreset _in	Input	Async	1 × Num. channels	Connects to RXDFELPMRESET on transceiver channel primitives
gt_rxlpmen_in	Input	rxusrclk2	1 × Num. channels	Connects to RXLPMEN on transceiver channel primitives
gt_txprecursor_i n	Input	Async	5 × Num. channels	Connects to TXPRECURSOR on transceiver channel primitives
gt_txpostcursor_i n	Input	Async	5 × Num. channels	Connects to TXPOSTCURSOR on transceiver channel primitives
gt_txdiffctrl_in	Input	txusrclk2	4 × Num. channels	Connects to TXDIFFCTRL on transceiver channel primitives
gt_txprbsforceer r_in	Input	txusrclk2	1 × Num. channels	Connects to TXPRBSFORCEERR on transceiver channel primitives
gt_txprbssel_in	Input	txusrclk	4 × Num. channels	Connects to TXPRBSSEL on transceiver channel primitives
gt_rxprbssel_in	Input	rxusrclk2	4 × Num. channels	Connects to RXPRBSSEL on transceiver channel primitives
gt_rxprbserr_out	Output	rxusrclk2	1 × Num. channels	Connects to RXPRBSERR on transceiver channel primitives
gt_rxprbscntrese t_in	Input	rxusrclk2	1 × Num. channels	Connects to RXPRBSCNTRESET on transceiver channel primitives
gt_rxcdrhold_in	Input	Async	1 × Num. channels	Connects to RXCDRHOLD on transceiver channel primitives
gt_dmonitorout_ out	Output	Async	17 × Num. channels	Connects to DMONITOROUT on transceiver channel primitives
gt_rxdisperr_out	Output	rxusrclk2	1 × Num. channels	Indicates the corresponding byte shown on rxdata has a disparity error. The rxdisperr pin of the transceiver is connected to this port.
Notes: 1.Each port is prefixed with gt<lane>_ where lane is from 0 to Num. channels -1

Table: GTP Transceiver Debug Ports shows transceiver debug ports that are available in all protocol templates for GTP transceivers.

Table 2-7: GTP Transceiver Debug Ports
Name	Direction	Clock Domain	Width	Description
DRP
drpclk_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPCLK on transceiver channel
drpaddr_in	Input	drp_clk_in	drp_addr_width x Num. channels	Connects to DRPADDR on transceiver channel primitives. See 7-series Architecture GTX/ GTH Transceivers User Guide(UG476) for more information on drp_addr_width.
drpdi_in	Input	drp_clk_in	16 × Num. channels	Connects to DRPDI on transceiver channel primitives
drpen_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPEN on transceiver channel primitives
drpwe_in	Input	drp_clk_in	1 × Num. channels	Connects to DRPWE on transceiver channel primitives
drpdo_out	Output	drp_clk_in	1 × Num. channels	Connects to DRPDO on transceiver channel primitives
drprdy_out	Output	drp_clk_in	1 × Num. channels	Connects to DRPRDY on transceiver channel primitives
TX reset and Initialization
gt_gttxreset_in	Input	sysclk_in	1 × Num. channels	Connects to GTTXRESET on transceiver channel primitives
gt_txpmareset_in	Input	Async	1 × Num. channels	Resets the TX PMA. Driven High, then deasserted to start the TX PMA reset process. Activating this port resets both the TX PMA and the TX PCS.
gt_txpcsreset_in	Input	Async	1 × Num. channels	Resets the TX PCS. Driven High, then deasserted to start the PCS reset process. Activating this port only resets the TX PCS.
gt_txuserrdy_in	Input	Async	1 × Num. channels	Connects to TXUSERRDY on transceiver channel primitives
gt_txresetdone_ out	Output	txusrclk2_in	1 × Num. channels	Indicates the GTX/GTH transceiver TX has finished reset and is ready for use. Driven Low when gttxreset goes High and not driven High until the GTX/GTH transceiver TX detects txuserrdy High.
RX reset and Initialization
gt_gtrxreset_in	Input	sysclk_in	1 × Num. channels	Connects to GTRXRESET on transceiver channel primitives.
gt_rxpmareset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX PMA reset process.
gt_rxpcsreset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX PMA reset process. The rxpcsreset signal does not start the reset process until rxuserrdy is High.
gt_rxbufreset_in	Input	Async	1 × Num. channels	Driven High, then deasserted to start the RX elastic buffer reset process. In either single or sequential mode, activating rxbufreset resets the RX elastic buffer only.
gt_rxuserrdy_in	Input	Async	1 × Num. channels	Connects to RXUSERRDY on transceiver channel primitives
gt_rxpmaresetdo ne_out	Output	-	1 × Num. channels	Indicates that the RX PMA reset is complete. Driven Low when GTRXRESET or RXPMARESET is asserted. Available for duplex and RX-only simplex configurations. Available only with GTH transceivers.
gt_rxresetdone_ out	Output	rxusrclk2	1 × Num. channels	When asserted, indicates the GTX/GTH transceiver RX has finished reset and is ready for use. Driven Low when gtrxreset is driven High. Not driven High until rxuserrdy goes High.
Clocking
gt_txbufstatus_o ut	Output	txusrclk2	2 × Num. channels	txbufstatus[1]: TX buffer overflow or underflow status. When txbufstatus[1] is set High, the signal remains High until the TX buffer is reset. 1: TX FIFO has overflow or underflow. 0: No TX FIFO overflow or underflow error. txbufstatus[0]: TX buffer fullness. 1: TX FIFO is at least half full. 0: TX FIFO is less than half full.
gt_rxbufstatus_o ut	Output	rxusrclk2	3 × Num. channels	RX buffer status. 000b: Nominal condition. 001b: Number of bytes in the buffer are less than CLK_COR_MIN_LAT. 010b: Number of bytes in the buffer are greater than CLK_COR_MAX_LAT. 101b: RX elastic buffer underflow. 110b: RX elastic buffer overflow.
gt_txphaligndon e_out	Output	Async	1 × Num. channels	Connects to TXPHALIGNDONE on transceiver channel primitives
gt_txphinitdone_ out	Output	Async	1 × Num. channels	Connects to TXPHINITDONE on transceiver channel primitives
gt_txdlysresetdo ne_out	Output	Async	1 × Num. channels	Connects to TXDLYSRESETDONE on transceiver channel primitives
gt_rxphaligndon e_out	Output	Async	1 × Num. channels	Connects to RXPHALIGNDONE of transceiver channel primitives
gt_rxdlysresetdo ne_out	Output	Async	1 × Num. channels	Connects to RXDLYSRESETDONE of transceiver channel primitives
gt_rxsyncdone_o ut	Output	Async	1 × Num. channels	Connects to RXSYNCDONE of transceiver channel primitives
pll0lock_out	Output	Async	1 × Num. channels	PLL0LOCK and PLL1LOCK of the 7 series FPGA GTP transceiver COMMON block. Available shared logic is in core.
pll1lock_out	Output	Async	1 × Num. channels	PLL0LOCK and PLL1LOCK of the 7 series FPGA GTP transceiver COMMON block. Available shared logic is in core.
Signal Integrity and Functionality
gt_eyescantrigge r_in	Input	rxusrclk2	1 × Num. channels	Connects to EYESCANTRIGGER on transceiver channel primitives
gt_eyescanreset_ in	Input	Async	1 × Num. channels	Connects to EYESCANRESET on transceiver channel primitives
gt_eyescandatae rror_out	Output	Async	1 × Num. channels	Connects to EYESCANDATAERROR on transceiver channel primitives
gt_loopback_in	Input	Async	3 × Num. channels	Connects to LOOPBACK on transceiver channel primitives
gt_rxpolarity_in	Input	rxusrclk2	1 × Num. channels	Connects to RXPOLARITY on transceiver channel primitives
gt_txpolarity_in	Input	txusrclk2	1 × Num. channels	Connects to TXPOLARITY on transceiver channel primitives
gt_rxlpmreset_in	Input	Async	1 × Num. channels	Resets the LPM circuitry.
gt_rxlpmhfhold_i n	Input	RXUSRCLK2	1 × Num. channels	When set to 1'b1, the current value of the high-frequency boost is held. When set to 1'b0, the high-frequency boost is adapted.
gt_rxlpmhfoverd en_in	Input	RXUSRCLK2	1 × Num. channels	When set to 1'b1, the high-frequency boost is controlled by the RXLPM_HF_CFG attribute. When set to 1'b0, the high-frequency boost is controlled by the rxlpmhfhold signal.
gt_rxlpmlfhold_i n	Input	Async	1 × Num. channels	When set to 1'b1, the current value of the low-frequency boost is held. When set to 1'b0, the low-frequency boost is adapted.
gt_txprecursor_i n	Input	Async	5 × Num. channels	Connects to TXPRECURSOR on transceiver channel primitives
gt_txpostcursor_i n	Input	Async	5 × Num. channels	Connects to TXPOSTCURSOR on transceiver channel primitives
gt_txdiffctrl_in	Input	txusrclk2	4 × Num. channels	Connects to TXDIFFCTRL on transceiver channel primitives
gt_txprbsforceer r_in	Input	txusrclk2	1 × Num. channels	Connects to TXPRBSFORCEERR on transceiver channel primitives
gt_txprbssel_in	Input	txusrclk	4 × Num. channels	Connects to TXPRBSSEL on transceiver channel primitives
gt_rxprbssel_in	Input	rxusrclk2	4 × Num. channels	Connects to RXPRBSSEL on transceiver channel primitives
gt_rxprbserr_out	Output	rxusrclk2	1 × Num. channels	Connects to RXPRBSERR on transceiver channel primitives
gt_rxprbscntrese t_in	Input	rxusrclk2	1 × Num. channels	Connects to RXPRBSCNTRESET on transceiver channel primitives
gt_rxcdrhold_in	Input	Async	1 × Num. channels	Connects to RXCDRHOLD on transceiver channel primitives
gt_dmonitorout_ out	Output	Async	1 × Num. channels	Connects to DMONITOROUT on transceiver channel primitives
gt_rxdisperr_out	Output	rxusrclk2	1 × Num. channels	Indicates the corresponding byte shown on rxdata has a disparity error. The rxdisperr pin of the transceiver is connected to this port.
gt_rxnotintable_ out	Output	rxusrclk2	1 × Num. channels	Indicates the corresponding byte shown on rxdata was not a valid character in the 8B/10B table. rxNotintable pin of the transceiver is connected to this port.
gt_rxcommadet_ out	Output	rxusrclk2	1 × Num. channels	This signal is asserted when the comma alignment block detects a comma. The assertion occurs several cycles before the comma is available at the FPGA RX interface. 0: Comma not detected 1: Comma detected
Notes: 1.Each port is prefixed with gt<lane>_ where lane is from 0 to Num. channels -1.

Port Descriptions - Port Descriptions - 3.6 English - PG168

7 Series FPGAs Transceivers Wizard (PG168)