•Creates customized HDL wrappers to configure high-speed serial transceivers in 7 series FPGAs.
•Automatically configures analog settings.
•Predefined templates are provided for Aurora 8B/10B, Aurora 64B/66B, CEI-6G, DisplayPort, Interlaken, Open Base Station Architecture Initiative (OBSAI), OC192, OC48, SRIO, 10GBASE-R, Common Packet Radio Interface (CPRI), Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), RXAUI, and XLAUI, OTU3, 10GH Small Form-factor Pluggable Plus (SFP+), Optical Transport Network OTU3, V-by-One, SDI, and others as well as custom protocol using start from scratch.
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Core Specifics |
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Supported Device Family(1) |
Artix®-7, Kintex®-7, and Virtex®-7 FPGAs, and Zynq SoCs |
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Supported User Interfaces |
Not Applicable |
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Resources |
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Provided with Core |
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Design Files |
RTL |
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Example Design |
Verilog and VHDL (Only Verilog is supported for GTZ transceivers) |
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Test Bench |
Verilog and VHDL (Only Verilog is supported for GTZ transceivers) |
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Constraints File |
XDC |
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Simulation Model |
None |
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Supported |
Not Applicable |
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Tested Design Flows(2) |
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Design Entry |
Vivado Design Suite |
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Simulation |
For supported simulators, see the |
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Synthesis |
Vivado Synthesis. |
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Support |
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Release Notes and Known Issues |
Master Answer Records: 54691 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Xilinx Support web page |
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Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.For the supported versions of the tools, see the |
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