The clocks mentioned in Table: Clock Signals are to be driven for proper operation of the example design.
Table 3-1: Clock Signals
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Clock
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Description
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GTREFCLK_PAD_N_IN/
GTREFCLK_PAD_P_IN
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External differential clock input pin pair for the reference clock of the 7 series FPGA transceiver Quad.
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DRP_CLK_IN_P/
DRP_CLK_IN_N
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External differential clock input pin pair for the DRP interface clock. This clock needs to be constrained in the XDC. See the 7 series data sheets for more information.
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SYSCLK
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Free running system/board clock is used to drive the FPGA logic in the example design. When the DRP interface is enabled, DRP_CLK is connected to SYSCLK in the example design. This clock needs to be constrained in the XDC.
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PLLLOCKDETCLK
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Stable reference clock for the detection of the feedback and reference clock signals to the PLL. The input reference clock to the PLL or any output clock generated from the PLL (for example, TXOUTCLK) must not be used to drive this clock.
This clock is required only when using the PLLFBCLKLOST and PLLREFCLKLOST ports. It does not affect the PLL lock detection, reset, and powerdown functions.
PLL indicates the CPLL/QPLL for GTX/GTH transceivers and PLL0/PLL1 for GTP transceivers. In the example design, PLLLOCKDETCLK is connected to DRPCLK or SYSCLK. PLLREFCLKLOST is used in the TX/RX StartUp FSM modules.
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