| 12/17/2025 Version
4.1 |
|
IO Delay Calibration Ports for Ethernet RGMII Interface
|
Updated this section. |
|
Constraining the Core
|
Updated this section. |
| 06/15/2022 Version
4.1 |
|
|
Table 1
|
Added this table. |
| 01/21/2021 Version
4.1 |
| Global updates |
Updated the entire document for Versal device. |
| 06/03/2020 Version
4.1 |
|
Product Specification
|
Updated this section to add new register information. |
| 063/06/2018 Version
4.0 |
| Global updates |
Added placement requirement for rgmii_rxc pin for Zynq
devices |
| 10/04/2017 Version
4.0 |
| Global updates |
Updated the frequency information of the CLKIN pin. |
| 04/06/2016 Version
4.0 |
|
Table 1
|
Updated this table to add description for mmcm_locked_in and
mmcm_locked_out signals. |
| N/A |
Added a note to indicate the exclusion of support for PHY Address 0. |
| 11/18/2015 Version
4.0 |
| Global updates |
Added support for Zynq UltraScale+ MP SoCs. |
| 06/24/2015 Version
4.0 |
|
Design Flow Steps
|
Updated the required constraints section. |
| 04/01/2015 Version
4.0 |
| Global updates |
- Removed XST
- Updated Table 2-1: Zynq-7000 Device Utilization
- Updated and added gmii_tx_clk_90 in Table 2-2: I/O Signals
- Updated Fig. 2-2: Interface of GMII to RGMII Core and Fig. 2-3: GMII to RGMII
Block Level
-
Updated and added gmii_clk_90, gmii_clk_90_out, gmii_clk_125m_90_out,
gmii_clk_25m_90_out, gmii_clk_2_5m_90_out, gmii_clk_125m_90_in,
gmii_clk_25m_90_in, mmcm_locked, and gmii_clk_2_5m_90_in in Table 2-3: Block
Level I/O Signals
- Updated description in General Design Guidelines section
- Updated Fig. 3-3: When Shared Logic in Core is Selected to Fig. 3-8: RGMII
Transmit Clock to the External PHY Device
- Updated Fig. 4-1: Core Customization Screen and Fig. 4-2: Shared Logic
Options
- Added User Parameters
- Added gmii_clk_90 in Clock Frequencies
- Added Parameter Changes from v3.0 to v4.0 and Port Changes from v3.0 to
v4.0
- Added UNISIM important note in Simulation section
- Updated RGMII_TXC_SKEW and related changes
|
| 10/01/2014 Version
3.0 |
| Global updates |
- Added interfaces for block level of IP and updated interfaces for core
level
- Added Chapter 6, Test Bench
- Added RGMII TXC skew adjustment constraints to Required Constraints
|
| 10/02/2013 Version
3.0 |
| Global updates |
- Revision number advanced to 3.0 to align with the core version
number.
- Updated numbers and text in Resource Utilization section.
- Updated Table 1 table.
- Replaced Table 3-1 with new table.
- Added Shared Logic section to Chapter 3.
- Update Figures 2-1, 2-2, 2-3, 3-3, 4-1, 4-2, 5-1, B-1, and
B-2
- Removed PHY Address section from Chapter 4.
- Removed Chapter 6, Simulation, Chapter 7, Synthesis and
Implementation, Chapter 8, Example Design, and Chapter 9, Test Bench.
- Added the section MDIO Management System to Chapter 2.
- Added Upgrading in the Vivado Design Suite section to Appendix
A.
|
| 03/20/2013 Version
1.0 |
| N/A |
Initial release. Based on PB014. |