RGMII Transmit Clock to the External PHY Device - RGMII Transmit Clock to the External PHY Device - 4.1 English - PG160

The following figure depicts how the RGMII TX clock output to the External PHY device is generated using an Output DDR buffer (ODDR). The RGMII v2.0 standard specifies that the TX clock to have a setup of 2 ns with respect to the TX data. This core gives you an option to either enable or disable this 2 ns skew between the TX clock and TX data. If the skew is enabled (RGMII_TXC_SKEW = 1), the RGMII TX clock is passed through the ODELAY2 primitive. If the skew is enabled (RGMII_TXC_SKEW = 2), the 90° phase-shifted gmii_tx_clk is used, and the output of ODDR is given out as rgmii_txc.