RGMII Transmission and Reception - RGMII Transmission and Reception - 4.1 English - PG160

GMII to RGMII v4.1 LogiCORE IP Product Guide (PG160)

Document ID
PG160
Release Date
2025-12-17
Version
4.1 English

Normal outbound frame transfer timing is illustrated in the following figure.

Figure 1. RGMII Normal Frame Transmission
LogiCORE IP GMII to RGMII Product Guide Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 gmii_txd_chx[7:0] rgmii_txc Sheet.15 gmii_txd_chx[7:0] rgmii_txd[3:0][7:4] Sheet.16 3:0 3:0 Sheet.17 7:4 7:4 Sheet.18 gmii_txd_chx[7:0] rgmii_tx_ctl Sheet.19 tx_en tx_en Sheet.20 tx_err tx_err Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sheet.104 Sheet.105 Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.112 Sheet.113 X13273 X13273

Normal inbound frame transfer timing is illustrated in the following figure.

Figure 2. RGMII Normal Frame Reception
LogiCORE IP GMII to RGMII Product Guide Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 gmii_txd_chx[7:0] rgmii_rxc Sheet.15 gmii_txd_chx[7:0] rgmii_rxd[3:0][7:4] Sheet.16 3:0 3:0 Sheet.17 7:4 7:4 Sheet.18 gmii_txd_chx[7:0] rgmii_rx_ctl Sheet.19 rx_dv rx_dv Sheet.20 rx_err rx_err Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 Sheet.104 Sheet.105 Sheet.106 Sheet.107 Sheet.108 Sheet.109 Sheet.110 Sheet.111 Sheet.112 Sheet.113 X13269 X13269

Multiplexing of data and control information is done by using both edges of the reference clocks and sending the lower 4 bits on the rising edge and the upper 4 bits on the falling edge. Control signals can be multiplexed into a single clock cycle using the same technique.