Normal outbound frame transfer timing is illustrated in the following figure.
Figure 1. RGMII Normal Frame Transmission
LogiCORE IP GMII to RGMII Product Guide
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gmii_txd_chx[7:0]
rgmii_txc
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gmii_txd_chx[7:0]
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tx_en
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tx_err
tx_err
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X13273
X13273
Normal inbound frame transfer timing is illustrated in the following figure.
Figure 2. RGMII Normal Frame Reception
LogiCORE IP GMII to RGMII Product Guide
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gmii_txd_chx[7:0]
rgmii_rxc
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X13269
X13269
Multiplexing of data and control information is done by using both edges of the reference
clocks and sending the lower 4 bits on the rising edge and the upper 4 bits on the
falling edge. Control signals can be multiplexed into a single clock cycle using the
same technique.