The following figure depicts the clocking scheme for RGMII RX clock input. The
rgmii_rxc clock input is driven through a BUFG, which is used to
clock the RX datapath in the core. This clock is also an output from this IP, and it is
used as the RX clock on the GEM GMII interface. The rgmii_rxc clock
input must be placed on a clock capable pin in Zynq devices.
Figure 1. RGMII Receive Clock from the External PHY Device
