The following figure illustrates the connection of the Gigabit Ethernet Controller in the AMD Zynq™ 7000 SoC to the GMII to RGMII core. The same
connection is applicable for AMD Zynq™
UltraScale+™ MPSoC too.
Figure 1. Core Block
Diagram
Important: The MDIO interface is necessary for the operation
of the core because the auto-negotiated speed of operation from the PHY is communicated to the
Ethernet MAC through MDIO.
The clock input is 200 MHz for AMD Zynq™ 7000, 300 MHz
for AMD Versal™
devices, and 375 MHz for Zynq UltraScale+ MPSoC. It is used as a reference clock for the IDELAYCTRL elements
and input for the management modules.
If the GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0), this
200/300/375 MHz clock is the input clock to the MMCM from which the TX clocks for all line
rates (125/12.5/ 2.5 MHz for 1000/100/10 Mb/s, respectively) are generated.