MDIO Bus System - MDIO Bus System - 4.1 English - PG160

GMII to RGMII v4.1 LogiCORE IP Product Guide (PG160)

Document ID
PG160
Release Date
2025-12-17
Version
4.1 English

The MDIO interface for 1 Gb/s operation (and slower speeds) is defined in IEEE 802.3-2012, clause 22. The following figure illustrates an example of MDIO bus system. This two-wire interface consists of a clock (MDC) and a shared serial data line (MDIO). The maximum permitted frequency of MDC is set at 2.5 MHz. An Ethernet MAC is shown as the MDIO bus master (the Station Management (STA) entity). Two PHY devices are shown connected to the same bus, both of which are MDIO slaves (MDIO Managed Device (MMD) entities).

Figure 1. Typical MDIO Managed System Layer_1 Sheet.1 Sheet.2 Sheet.3 Host Host Sheet.4 Bus IF Bus IF Sheet.5 Sheet.6 MDIO MDIO Sheet.7 Master Master Sheet.8 Sheet.9 MAC (STA) MAC (STA) Sheet.10 Sheet.11 Sheet.12 Sheet.13 MDIO MDIO Sheet.14 Slave Slave Sheet.15 Sheet.16 Sheet.17 Sheet.18 Configuration Configuration Sheet.19 Register Register Sheet.20 0 to 31 0 to 31 Sheet.21 ( ( Sheet.22 REGAD) REGAD) Sheet.23 PHY1 (MMD) PHY1 (MMD) Sheet.24 Sheet.25 Sheet.26 Sheet.27 MDIO MDIO Sheet.28 Slave Slave Sheet.29 Sheet.30 Sheet.31 Sheet.32 Configuration Configuration Sheet.33 Register Register Sheet.34 0 to 31 0 to 31 Sheet.35 ( ( Sheet.36 REGAD) REGAD) Sheet.37 PHY2 (MMD) PHY2 (MMD) Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Physical Address Physical Address Sheet.51 ( ( Sheet.52 PHYAD = 1) PHYAD = 1) Sheet.53 Sheet.54 Physical Address Physical Address Sheet.55 ( ( Sheet.56 PHYAD = 2) PHYAD = 2) Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75

The MDIO bus system is a standardized interface for accessing the configuration and status registers of Ethernet PHY devices. In the example illustrated, the Management Host Bus I/F of the Ethernet MAC can access the configuration and status registers of two PHY devices through the MDIO bus.