This clock is used by the transmit circuitry of the core. It is also an output
from this core, and it is used as the TX clock on the GEM GMII interface. The
Shared Logic option determines if clock resources are used
for this clock. If shared logic is in the core, then clock resources are used. If the
shared logic is in the example design, then no clocking resources are used.
This clock can be sourced externally or can be generated internally within the core. The
VHDL generic C_EXTERNAL_CLOCK is used to indicate this choice. The following paragraphs
describe the clocking scheme in both the cases, that is, when shared logic is in the
core and when shared logic is in the example design.
Figure 1. GMII Clock Sourced Externally and Shared Logic in Core
The preceding figure depicts the clocking scheme when the GMII clock is sourced
externally and the Shared Logic in Core option is selected. This
mode is active when the VHDL generic C_EXTERNAL_CLOCK is set to 1. In this case, you
must ensure that the GMII clock frequency is appropriate for the line rate. That is, it
should be 2.5 MHz for 10 Mb/s, 25 MHz for 100 Mb/s and 125 MHz for 1,000 Mb/s. The
external GMII clock is routed through the global clock buffer (BUFG) and then used in
the core.
The clock, gmii_clk_out, is also an output of this IP that can be used
by other instances of the GMII to RGMII cores, which are configured for the shared logic
to be present in the example design. This allows the sharing of the clock resources.
gmii_clk_90 is gmii_clock phase shifted by 90°. The
logic in the dotted area is generated only if the option to add 2 ns skew on
rgmii_txc by using MMCM is selected.
Figure 2. GMII Clock Sourced Internally and Shared Logic in Core
The preceding figure depicts the clocking scheme when the GMII clock is sourced
internally and the Shared Logic in Core option is selected. This
mode is active when the VHDL generic C_EXTERNAL_CLOCK is set to 0. The GMII to RGMII
core has a built-in clock generator for providing 2.5 MHz, 25 MHz, and 125 MHz frequency
clocks for 10 Mb/s, 100 Mb/s, and 1 Gb/s speeds of operation, respectively. The clock
generator uses an MMCM to generate the clocks for all three line-rates. The block
wrapper has the clock multiplexers (BUFGMUX) that are used to switch between three
different clock frequencies for the three different speed modes of the MAC. The speed_mode(0) and speed_mode(1) signals are used as selection pins of BUFGMUX0 and BUFGMUX1,
respectively.
The clocks shown in the gray area are only generated when the option to add 2 ns skew on
rgmii_txc through MMCM. These clocks are generated to have a phase
shift of 90°.
The three clocks, gmii_clk_2_5m_out, gmii_clk_25m_out,
and gmii_clk_125m_out, are also outputs of this IP core that can be
used by other instances of the GMII to RGMII cores, which are configured for the shared
logic to be present in the example design. This allows the sharing of the clock
resources.
Figure 3. Clock Sourced Externally and Shared Logic in Example
Design
The preceding figure depicts the clocking scheme when the GMII clock is sourced
externally, and the Shared Logic in Example Design is selected. In this case, no
clocking resources are used by the core. The gmii_clk signal is the output of another
GMII to RGMII core, which is configured for the shared logic to be present in the
core.
Figure 4. GMII Clock Sourced Internally and Shared Logic in Example
Design
The preceding figure depicts the clocking scheme when the GMII clock is sourced
internally, and the Shared Logic in Example Design is selected. In this case, the only
clock resources used by the core are the two clock multiplexers. The block wrapper has
the clock multiplexers (BUFGMUX) that are used to switch between three different clock
frequencies for the three different speed modes of the MAC. The speed_mode(0) and speed_mode(1) signals
are used as selection pins of BUFGMUX0 and BUFGMUX1, respectively.