Constraining the Core - Constraining the Core - 4.1 English - PG160

Required Constraints

The GMII to RGMII core requires design constraints to guarantee maximum performance.

Vivado Design Suite

These constraints should be placed in an XDC file at the top level of the design. The example of the constraint text shown in the following paragraphs is based on the port names of the GMII to RGMII core. If these ports are mapped to FPGA pin names that are different, the FPGA pin names should be submitted for the port names in the following example.

# Clock Period Constraints
create_clock -period 5.000 -name clkin -add [get_nets clkin]
create_clock -period 8.000 -name rgmii_rxc -add [get_ports rxc]
# Clock constraint if parameter C_EXTERNAL_CLOCK = 1
create_clock -add -name gmii_clk -period 8.000 [get_ports gmii_clk]
# Clock constraint if parameter C_EXTERNAL_CLOCK = 1 and clock skew on TXC is through
MMCM
create_clock -add -name gmii_clk_90 -period 8.000 -waveform {2 6} [get_ports
gmii_clk_90]
#False path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/
*reset_sync*/PRE }]
set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/
SYNC_*/data_sync* }] -filter { name =~ *D }]
set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
#False path constraints from Control Register outputs
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/
DUPLEX_MODE_REG*/C }]
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/
SPEED_SELECTION_REG*/C }]
# constraint valid if parameter C_EXTERNAL_CLOCK = 0
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE0}]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S0}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE1}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S1}]
# constraint valid if parameter C_EXTERNAL_CLOCK = 0 and clock skew on TXC is through
MMCM
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE0}]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S0}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE1}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S1}]
#IO Placement
set_property PACKAGE_PIN D18 [get_ports clkin_p]
set_property PACKAGE_PIN C19 [get_ports clkin_n]
set_property IOSTANDARD LVDS_25 [get_ports clkin_p]
set_property IOSTANDARD LVDS_25 [get_ports clkin_n]
set_property PACKAGE_PIN A18 [get_ports phy_reset_n]
set_property IOSTANDARD LVCMOS18 [get_ports phy_reset_n]
set_property PACKAGE_PIN N20 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN K19 [get_ports rgmii_txc]
set_property PACKAGE_PIN D20 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN N19 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN K20 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN L21 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN M22 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN M19 [get_ports rgmii_rxc]
set_property PACKAGE_PIN L22 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN M21 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN K21 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN N17 [get_ports {rgmii_rxd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_txd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN B19 [get_ports mdio_phy_mdc]
set_property PACKAGE_PIN C20 [get_ports mdio_phy_mdio]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_phy_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_phy_mdio]
# These constraints are for non-Versal devices
# To Adjust GMII Rx Input Setup/Hold Timing
# IDELAY_VALUE and DELAY_VALUE support depends on the device family
# IDELAY_VALUE is used for 7-series Zynq devices
# DELAY_VALUE is used for Zynq UltraScale+ devices
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~
*delay_rgmii_rx_ctl}]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~
*delay_rgmii_rxd*}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *idelayctrl}]

If the option is selected to provide 2 ns skew to RGMII TXC in devices supporting HPIO banks, these constraints can be added to fine-tune the delay:

#These constraints are for non-Versal devices
#To adjust RGMII TXC delay when 2 ns skew option is selected
set_property ODELAY_VALUE "26" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_txc}]
set_property ODELAY_VALUE "0" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_tx_ctl*}]
set_property ODELAY_VALUE "0" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_txd*}]
set_property IODELAY_GROUP "gpr1" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_txc}]
set_property IODELAY_GROUP "gpr1" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_tx_ctl*}]
set_property IODELAY_GROUP "gpr1" [get_cells -hier -filter {name =~ *_core/
*oddr_rgmii_txd*}]
# Use these constraints to modify input delay on RGMII signals
set_input_delay -clock [get_clocks <core_instance>_rgmii_rx_clk] -max -1.5
[get_ports {rgmii_rxd[*] rgmii_rx_ctl}]
set_input_delay -clock [get_clocks <core_instance>_rgmii_rx_clk] -min -2.8
[get_ports {rgmii_rxd[*] rgmii_rx_ctl}]
set_input_delay -clock [get_clocks <core_instance>_rgmii_rx_clk] -clock_fall -max
-1.5 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}]
set_input_delay -clock [get_clocks <core_instance>_rgmii_rx_clk] -clock_fall -min
-2.8 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}]
# Use these constraints to modify output delay on RGMII signals if 2ns delay is added
by the core
set_output_delay 0.75 -max -clock [get_clocks <core_instance>_rgmii_tx_clk] [get_ports {rgmii_txd[*]
rgmii_tx_ctl}]
set_output_delay -0.7 -min -clock [get_clocks <core_instance>_rgmii_tx_clk] [get_ports {rgmii_txd[*]
rgmii_tx_ctl}]
set_output_delay 0.75 -max -clock [get_clocks <core_instance>_rgmii_tx_clk] [get_ports {rgmii_txd[*]
rgmii_tx_ctl}] -clock_fall -add_delay
set_output_delay -0.7 -min -clock [get_clocks <core_instance>_rgmii_tx_clk] [get_ports {rgmii_txd[*]
rgmii_tx_ctl}] -clock_fall -add_delay
# Use these constraints to modify output delay on RGMII signals if 2ns delay is added
by external PHY
set_output_delay -clock [get_clocks <core_instance>_rgmii_tx_clk] -max -1.0 [get_ports {rgmii_txd[*]
rgmii_tx_ctl}]
set_output_delay -clock [get_clocks <core_instance>_rgmii_tx_clk] -min -2.6 [get_ports {rgmii_txd[*]
rgmii_tx_ctl}] -add_delay
set_output_delay -clock [get_clocks <core_instance>_rgmii_tx_clk] -clock_fall -max -1.0 [get_ports
{rgmii_txd[*] rgmii_tx_ctl}]
set_output_delay -clock [get_clocks <core_instance>_rgmii_tx_clk] -clock_fall -min -2.6 [get_ports
{rgmii_txd[*] rgmii_tx_ctl}]

The above constraints can be modified to allow the tool to meet timing. Use the following constraint to modify the slew in the IOB:

set_property slew FAST [get_ports [list {rgmii_txd[3]} {rgmii_txd[2]} {rgmii_txd[1]}
{rgmii_txd[0]} rgmii_txc rgmii_tx_ctl]]

The MMCM can be used to generate GMII clocks when C_EXTERNAL_CLOCK is set to 0. For more information, see Figure 2. The MMCM settings are based on the CLKIN1 pin of the MMCM, which has a frequency of 200 MHz for Zynq 7000 and 375 MHz for Zynq UltraScale+ MPSoC. If any other frequencies are used, update using the following constraints. Use the following example for Zynq UltraScale+ MPSoC.

set_property DIVCLK_DIVIDE {1} [get_cells -hier -regexp -nocase {.*gmii.*mmcm.*}]
set_property CLKIN1_PERIOD {2.667} [get_cells -hier -regexp -nocase
{.*gmii.*mmcm.*}]
set_property CLKFBOUT_MULT_F {8.000} [get_cells -hier -regexp -nocase
{.*gmii.*mmcm.*}]
set_property CLKOUT1_DIVIDE {40} [get_cells -hier -regexp -nocase {.*gmii.*mmcm.*}]
set_property CLKOUT2_DIVIDE {40} [get_cells -hier -regexp -nocase {.*gmii.*mmcm.*}]

Device, Package, and Speed Grade Selections

The core can be implemented in an AMD Zynq™ 7000 SoC device with these attributes:

• Is large enough to accommodate the core
• Contains a sufficient number of IOBs
• Has a supported speed grade (–1 or faster)

Clock Frequencies

Following are clock frequency requirements:

clkin

200 MHz

gmii_clk

Present when the GMII clock is sourced externally) 2.5/25/125 MHz for 10/100/1000 Mb/s, respectively

gmii_clk_90

gmii_clk phase shifted by 90°

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

All ports should be given location constraints appropriate to your design, within banking limits.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

According to the RGMII v2.0 specification, the I/O pins must use 1.5V HSTL interface voltages. Like the majority of PHYs, those selected for AMD development boards are multi-standard and operate at either 1.8V or 2.5V.

A Tcl script that checks the I/O standard of RGMII is included with the IP and can be sourced post-implementation. The Tcl script is located at <project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/drc_check/io.

The following table provides information on I/O standards supported for different Zynq 7000 SoC devices that correspond to the AMD 7 series programmable logic equivalent.