This section describes the clocking scheme implemented in the core. There are three main clock inputs to this core, namely the 200/300/375 MHz free-running clock, the GMII transmit clock, and the RGMII receive clock.
This section describes the clocking scheme implemented in the core. There are three main clock inputs to this core, namely the 200/300/375 MHz free-running clock, the GMII transmit clock, and the RGMII receive clock.