Changes from v2.0 to v3.0 - Changes from v2.0 to v3.0 - 4.1 English - PG160

GMII to RGMII v4.1 LogiCORE IP Product Guide (PG160)
Document ID
PG160
Release Date
2025-12-17
Version
4.1 English

Parameter Changes

Table 1. Parameters Modified
Parameter Name Changes What to do
C_PHYADDR Data type changed from std_logic_vector to integer When mapping value to this parameter, use integer data type for the corresponding PHY Address
Table 2. Parameters Added
Parameter Name Description Default Value Allowable Values
C_RGMII_TXC_SKEW_EN Provide 2 ns skew on RGMII TXC with respect to RGMII TXD 0
  • 0 = rgmii_txc is edge aligned with respect to rgmii_txd
  • 1= rgmii_txc is delayed by 2 ns with respect to rgmii_txd
C_RGMII_TXC_ODELAY_VAL ODELAY value passed on to ODELAY2 primitive used to provide the skew on RGMII TXC 26 This is valid only when C_RGMII_TXC_SKEW_EN = 1. Specifies the ODELAY tap value to be used to provide skew on RGMII TXC

Port Changes

Table 3. Ports Deleted
Port Name and Width I/O Description What to do
clkin I 200 MHz Reference clock This port is replaced by ref_clk_in. Map the 200/375 MHz clock from the shared logic block/external source to this port
mdio_mdc I MDIO clock from GEM This port is replaced by mdio_gem_mdc. Connect the GEM mdc port to this port.
mdio_i O MDIO Input to GEM This port is replaced by mdio_gem_i. Connect the GEM mdio_i port to this port.
mdio_o I MDIO Output from GEM This port is replaced by mdio_gem_o. Connect the GEM mdio_o port to this port.
mdio_t I MDIO 3-state Input from GEM This port is replaced by mdio_gem_t. Connect the GEM mdio_t port to this port.
mdc O MDC clock to External PHY device This port is replaced by mdio_phy_mdc. Connect the PHY MDC port to this port.
mdio Bidirectional MDIO data line to External PHY device The core no longer instantiates the Bi-Di I/O primitive. Instead, it gives out the _i, _o, and _t signals, which should be connected to a Bi-Di I/O primitive. This primitive has to be user-instantiated.

The following ports were added to the core (non-shared logic).

Table 4. Ports Added
Port Name and Width I/O Description What to do
ref_clk_in I 200 MHz clock from the shared logic block to the core This should be driven by one of the following:
  • the shared logic provided with the core
  • by another cores shared logic block
  • from another cores shared logic block
  • from an external clock source
gmii_clk_125m_in I Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) 125 MHz GMII TX clock from the shared logic block to the core This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
gmii_clk_25m_in I Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) 25 MHz GMII TX clock from the shared logic block to the core This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
gmii_clk_2_5m_in I Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) 2.5 MHz GMII TX clock from the shared logic block to the core This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
mdio_phy_mdc O MDC clock to External PHY device Connect this to External PHY device MDC input.
mdio_phy_i I The _o output from the Bi-Di primitive on the MDIO Data line from the External PHY Device Connect this to the _o port of the Bi-Di I/O primitive on the MDIO to the External PHY device.
mdio_phy_o O The _i input to the Bi-Di primitive on the MDIO Data line from the External PHY Device Connect this to the _i port of the Bi-Di I/O primitive on the MDIO to the External PHY device.
mdio_phy_t O The _t input to the Bi-Di primitive on the MDIO Data line form the External PHY Device Connect this to the _t port of the Bi-Di I/O primitive on the MDIO to the External PHY device.