Changes from 3.0 to 4.0 - Changes from 3.0 to 4.0 - 4.1 English - PG160

GMII to RGMII v4.1 LogiCORE IP Product Guide (PG160)

Document ID: PG160
Release Date: 2025-12-17
Version: 4.1 English

Parameter Changes

Table 1. Parameters Removed
Parameter Name	Changes	What do do
C_RGMII_TXC_SKEW_EN	Parameter replaced with RGMII_TXC_SKEW	The previous mapping holds true for the new parameter.

Table 2. Parameter Added
Parameter Name	Description	Default Value	Allowable Values
RGMII_TXC_SKEW	Provide 2 ns skew on RGMII TXC with respect to RGMII TXD	0	0 = rgmii_txc is edge aligned with respect to rgmii_txd (that is, 2 ns delay added by external PHY) 1 = rgmii_txc is delayed by 2 ns with respect to rgmii_txd by ODELAY (available only in devices having HPIOs) 2 = rgmii_txc is delayed by 2 ns with respect to rgmii_txd by MMCM

Port Changes

Table 3. Port Changes
Port Name and Width	I/O	Description	What to do
gmii_clk_90	I	Present only when GMII clock is sourced externally (C_EXTERNAL_CLOCK = 1) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2). This is gmii_clk phase shifted by 90°.	This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
gmii_clk_125m_90_in	I	Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 125 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core	This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
gmii_clk_25m_90_in	I	Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 25 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core.	This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
gmii_clk_2_5m_90_in	I	Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 2.5 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core	This should be driven either by the shared logic provided with the core, or by another cores shared logic block.
mmcm_locked	O	Valid only for Shared Logic in Core configuration and if the external clock option is not selected. This indicates that the MMCM has locked.	Can be left open if not used.