s_axis_tx_tuser - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The following table shows the mapping between s_axis_rq_tuser from Requester Request interface and s_axis_tx_tuser signal bus from the AXI4-Stream (Basic) Transmit interface.

Table 1. Mapping between s_axis_rq_tuser and s_axis_tx_tuser
AXI4-Stream (Basic) Receive Interface Name Mnemonic AXI4-Stream (Enhanced) Requester Request Interface Name Mnemonic Comments
s_axis_tx_tuser[0] tx_ecrc_gen s_axis_rq_tdata[127] Force ECRC Same Functionality
s_axis_tx_tuser[1] tx_err_fwd s_axis_rq_tdata[79] Poisoned request

Same

Functionality

s_axis_tx_tuser[2] tx_str NA NA No Equivalent Signal
s_axis_tx_tuser[2] t_src_dsc s_axis_rq_tuser[11] Discontinue

Same

Functionality