s_axis_tx_tstrb - s_axis_tx_tstrb - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document_ID
PG156
Release_Date
2024-12-06
Version
4.4 English

Use s_axis_cc_tkeep with Byte Count Descriptor (s_axis_cc_tdata[28:16]) to indicate the byte enables for the last Dword of the payload.

The following table shows the mapping between s_axis_cc_tkeep from the Completer Completion interface and the s_axis_tx_tstrb signal bus from the AXI4-Stream (Basic) Transmit interface when tlast is not asserted.

Table 1. Mapping Between s_axis_cc_tkeep and s_axis_tx_tstrb
Interface Width s_axis_tx_tstrb s_axis_rq_tkeep
64 0x0F 0x1
0xFF 0x3
128 0x0F 0x1
0xFF 0x3
0xFFF 0x7
0xFFFF 0xF