s_axis_tx_tstrb - s_axis_tx_tstrb - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The following table shows the Requester Request interface signals used to generate the s_axis_tx_tstrb signal bus.

Table 1. Requester Request Interface Signals for m_axis_rx_tuser
AXI4-Stream Requester (Enhanced) Request Interface Name Mnemonic
s_axis_rq_tkeep  
s_axis_rq_tuser[3:0] first_be [3:0]
s_axis_rq_tuser[7:4] last_be [3:0]

The following table shows the mapping between s_axis_cc_tkeep from the Completer Completion interface and the s_axis_tx_tstrb signal bus from the AXI4-Stream (Basic) Transmit interface when tlast is not asserted.

Table 2. Mapping Between s_axis_cc_tkeep and s_axis_tx_tstrb
Interface Width s_axis_tx_tstrb s_axis_rq_tkeep
64 0x0F 0x1
0xFF 0x3
128 0x0F 0x1
0xFF 0x3
0xFFF 0x7
0xFFFF 0xF