Implementation Design Overview - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The implementation design consists of a simple PIO example that can accept read and write transactions and respond to requests, as illustrated in the following figure. Source code for the example is provided with the core. For more information about the PIO example design, see Programmed Input/Output: Endpoint Example Design.

Figure 1. Implementation Example Design Block Diagram