The following figure illustrates the user interface of the core.
The interface is organized as four separate interfaces through which data can be transferred between the PCIe link and the user application:
- A PCIe Completer Request (CQ) interface through which requests arriving from the link are delivered to the user application.
- A PCIe Completer Completion (CC) interface through which the user application can send back responses to the completer requests. The user application can process all Non-Posted transactions as split transactions. That is, it can continue to accept new requests on the completer request interface while sending a completion for a request.
- A PCIe Requester Request (RQ) interface through which the user application can generate requests to remote PCIe devices attached to the link.
- A PCIe Requester Completion (RC) interface through which the integrated block returns the completions received from the link (in response to the user application requests as PCIe requester) to the user application.
Each of the four interfaces is based on the AMBA4® AXI4-Stream Protocol Specification. The width of these interfaces can be configured as 64, 128, or 256 bytes, and the user clock frequencies can be selected as 62.5, 125, or 250 MHz, depending on the number of lanes and PCIe generation you choose.
The following table lists the valid combinations of interface width and user clock frequency for the different link widths and link speeds supported by the integrated block. All four AXI4-Stream interfaces are configured with the same width in all cases.
In addition, the integrated block contains the following interfaces through which status information is communicated to the PCIe master side of the user application:
- A flow control status interface attached to the requester request (RQ) interface that provides information on currently available transmit credit. This enables the user application to schedule requests based on available credit, avoiding blocking in the internal pipeline of the controller due to lack of credit from its link partner.
- A tag availability status interface attached to the requester request (RQ) interface that provides information on the number of tags available to assign to Non-Posted requests. This allows the client to schedule requests without the risk of being blocked when the tag management unit in the PCIe IP has exhausted all the tags available for outgoing Non-Posted requests.
- A receive message interface attached to the completer request (CQ) interface for delivery of message TLPs received from the link. It can optionally provide indications to the user logic when a message is received from the link (instead of transferring the entire message to the user application over the AXI4 interface).
| PCI Express Generation/Maximum Link Speed | Maximum Link Width Capability | AXI4-Stream Interface Width | User Clock Frequency (MHz) |
|---|---|---|---|
| Gen1 (2.5 GT/s) | x1 | 64 bits | 62.5, 125, or 250 |
| x2 | 64 bits | 62.5, 125, or 250 | |
| x4 | 64 bits | 125, or 250 | |
| x8 | 64 bits | 250 | |
| 128 bits | 125 | ||
| Gen2 (5.0 GT/s)\ | x1 | 64 bits | 62.5, 125, or 250 |
| x2 | 64 bits | 125, or 250 | |
| x4 | 64 bits | 250 | |
| 128 bits | 125 | ||
| x8 | 128 bits | 250 | |
| 256 bits | 125 | ||
| Gen3 (8.0 GT/s) | x1 | 64 bits | 125, or 250 |
| x2 | 64 bits | 250 | |
| 128 bits | 125 | ||
| x4 | 128 bits | 250 | |
| 256 bits | 125 | ||
| x8 | 256 bits | 250 | |
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