Completer Request Descriptor Formats - Completer Request Descriptor Formats - 4.4 English - PG156

This field is defined for memory transactions and Atomic Operations only. It contains the AT bits extracted from the TL header of the request.

00: Address in the request is untranslated

01: Transaction is a Translation Request

10: Address in the request is a translated address

11: Reserved

This field applies to memory, I/O, and Atomic Op requests. It provides the address from the TLP header. This is the address of the first Dword referenced by the request. The First_BE bits from m_axis_cq_tuser must be used to determine the byte-level address.

When the transaction specifies a 32-bit address, bits [63:32] of this field are 0.

These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 - 256 Dwords. For I/O accesses, the Dword count is always 1.

For a zero length memory read/write request, the Dword count is 1, with the First_BE bits set to all 0s.

PCI Requester ID associated with the request. With legacy interpretation of RIDs, these 16 bits are divided into an 8-bit bus number [95:88], 5-bit device number [87:83], and 3-bit Function number [82:80]. When ARI is enabled, bits [95:88] carry the 8-bit bus number and [87:80] provide the Function number.

When the request is a Non-Posted transaction, the user completer application must store this field and supply it back to the integrated block with the completion data.

This field is defined for memory, I/O, and Atomic Op requests only. It provides the Function number the request is targeted at, determined by the BAR check. When ARI is in use, all 8 bits of this field are valid. Otherwise, only bits [106:104] are valid.

Following are Target Function Value to PF/VF map mappings:

• 0: PF0
• 1: PF1
• 64: VF0
• 65: VF1
• 66: VF2
• 67: VF3
• 68: VF4
• 69: VF5

This field is defined for memory, I/O, and Atomic Op requests only. It provides the matching BAR number for the address in the request.

• 000: BAR 0 (VF-BAR 0 for VFs).
• 001: BAR 1 (VF-BAR 1 for VFs)
• 010: BAR 2 (VF-BAR 2 for VFs)
• 011: BAR 3 (VF-BAR 3 for VFs)
• 100: BAR 4 (VF-BAR 4 for VFs)
• 101: BAR 5 (VF-BAR 5 for VFs)
• 110: Expansion ROM Access
• 111: No BAR Check (Valid for Root Port only)

For 64-bit transactions, the BAR number is given as the lower address of the matching pair of BARs (that is, 0, 2, or 4).

This 6-bit field is defined for memory, I/O, and Atomic Op requests only. It provides the aperture setting of the BAR matching the request. This information is useful in determining the bits to be used in addressing its memory or I/O space. For example, a value of 12 indicates that the aperture of the matching BAR is 4K, and the user application can therefore ignore bits [63:12] of the address.

For VF BARs, the value provided on this output is based on the memory space consumed by a single VF covered by the BAR.

These bits provide the setting of the Attribute bits associated with the request. Bit 124 is the No Snoop bit and bit 125 is the Relaxed Ordering bit. Bit 126 is the ID-Based Ordering bit, and can be set only for memory requests and messages.

When the request is a Non-Posted transaction, the user completer application must store this field and supply it back to the integrated block with the completion data.

This field is defined for OBFF messages only. The OBFF Code field is used to distinguish between various OBFF cases:

• 1111b: CPU Active – System fully active for all device actions including bus mastering and interrupts
• 0001b: OBFF – System memory path available for device memory read/write bus master activities
• 0000b: Idle – System in an idle, low power state

All other codes are reserved.

This field is defined for all messages. It contains the 8-bit Message Code extracted from the TLP header.

Appendix F of the PCI Express Base Specification, rev. 3.0 provides a complete list of the supported Message Codes.