Architecture - Architecture - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The Endpoint model consists of these blocks:

  • PCI Express Endpoint (the core in Endpoint configuration) model.
  • PIO slave design, consisting of:
    • PIO_RX_ENGINE
    • PIO_TX_ENGINE
    • PIO_EP_MEM
    • PIO_TO_CTRL

The PIO_RX_ENGINE and PIO_TX_ENGINE blocks interface with the ep block for reception and transmission of TLPs from/to the Root Port Design Under Test (DUT). The Root Port DUT consists of the core configured as a Root Port and the Configurator Example Design, which consists of a Configurator block and a PIO Master design, or customer design.

The PIO slave design is described in detail in Programmed Input/Output: Endpoint Example Design.