When the AXI Quad SPI core is configured in XIP mode, only the following registers are available through the AXI4-Lite interface:
These 32-bit registers are configurable and accessible individually through the AXI4-Lite interface. The following table provides a summary of the AXI Quad SPI core registers in XIP mode.
|
Base Address Offset (hex) |
Register Name | Access Type | Default Value (hex) | Description |
|---|---|---|---|---|
| Core Grouping | ||||
| 60 | XIP Config_Reg (XIP-CR) | R/W | 0x0 | XIP configuration register |
| 64 | XIP Status_Reg (XIP-SR) | Read | 0x0 | XIP status register |
Important: In XIP mode, the AXI QUAD SPI does not generate
any interrupt. The interrupt pin can be left unconnected.