Write Enable Command Sequence - Write Enable Command Sequence - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2026-01-16
Version
3.2 English
  1. Disable the master transaction by asserting the master inhibit bit of SPICR (60h), and reset the RX and TX FIFOs through SPICR. Example: write 0x1E6 to SPICR.

    Example: write 0x1E6 to SPICR

  2. Issue the write enable command by writing 0x06 into SPIDTR.
  3. Issue chip select by writing 0x00 to SPISSR(70h).
  4. Enable master transaction by deasserting the SPICR master inhibit bit.
  5. Deassert chip select by writing 0x01 to SPISSR.
  6. Disable master transaction by asserting the SPICR master inhibit bit.