The Software Reset Register (SRR) permits resetting the core independently of other cores in the system.
Important: To activate the software-generated
reset, the value of
0x0000_000a must be written to the Software Reset
Register. Writing 0x0000_000a to the SRR resets the core
register for four AXI clock cycles. Any other write access generates undefined results and
results in an error. The bit assignment in the software reset register is shown in the
following figure and described in the following table. Any attempt to read this register
returns undefined data.
Figure 1. Software Reset Register (Core Base Address + 0x40)
| Bits | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 31:0 | Reset | Write only | N/A | The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core. |