Implementing the Example Design - Implementing the Example Design - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2026-01-16
Version
3.2 English

After following the steps described in Customizing and Generating the Core, implement the example design as follows:

  1. Right-click the core in the Hierarchy window, and select Open IP Example Design. A new window pops up where you can specify a new directory name for the example design, or keep the default directory.

    A new project is created in the selected directory and is opened in a new AMD Vivado™ window.

  2. In the Flow Navigator (left side pane), click Run Implementation and follow the directions.

In the current project directory, a new project called <component_name>_example is created. This directory and its subdirectories contain all the source files that are required to create the AXI Quad SPI example design.

The following figure shows the design files generated.

Table 1. Example Design Directory
Name Description
<component_name>_exdes.vhd Top-level HDL file for the example design.
memory.vhd Memory model used in XIP mode.
memory_model.vhd Memory model used in other modes.

The following table shows the COE files generated for data transmission.

Table 2. COE Design Directory
Name Description
qspi_addr_*.coe Delivers address information to the AXI Traffic Generator.
qspi_data_*.coe Delivers data information to the AXI Traffic Generator.
qspi_ctrl_*.coe Delivers control information to the AXI Traffic Generator.
qspi_mask_*.coe Delivers mask information to the AXI Traffic Generator.
init_data_coe Initialization data to BMG.
  1. The range from 1 to 3 as each file corresponds to a particular AXI Traffic Generator.

The following table shows the test bench file delivered.

Table 3. Simulation Directory
Name Description
<component_name>_exdes_tb.vhd Test bench for Exdes.

The following table shows the constraints file delivered.

Table 4. Constraints Directory
Name Description
exdes.xdc Top-level constraints file for the example design.

The example design has been verified on KC705 boards. Board constraints are also specified in the exdes.xdc file but are commented out by default.

Important: Uncomment the pin constraints while testing on the board.